From ad2611f9af42c7cc654106463dbb26de6ff3bfe4 Mon Sep 17 00:00:00 2001
From: Evan Hunt <each@isc.org>
Date: Tue, 19 Jul 2016 11:10:43 -0700
Subject: [PATCH] [master] fix isc_atomic_xadd() on MIPS

4414.	[bug]		Corrected a bug in the MIPS implementation of
			isc_atomic_xadd(). [RT #41965]

Submitted by Lamont Jones (lamont@debian.org). Closes Debian issue #406409.
---
 CHANGES                           |  3 ++
 lib/isc/mips/include/isc/atomic.h | 66 +++++++++++++++----------------
 2 files changed, 34 insertions(+), 35 deletions(-)

diff --git a/CHANGES b/CHANGES
index 7220de3810..72471910a5 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,3 +1,6 @@
+4414.	[bug]		Corrected a bug in the MIPS implementation of 
+			isc_atomic_xadd(). [RT #41965]
+
 4413.	[bug]		GSSAPI negotiation could fail if GSS_S_CONTINUE_NEEDED
 			was returned. [RT #42733]
 
diff --git a/lib/isc/mips/include/isc/atomic.h b/lib/isc/mips/include/isc/atomic.h
index 668884d244..1cc4793c62 100644
--- a/lib/isc/mips/include/isc/atomic.h
+++ b/lib/isc/mips/include/isc/atomic.h
@@ -23,18 +23,20 @@ static inline isc_int32_t
 isc_atomic_xadd(isc_int32_t *p, int val) {
 	isc_int32_t orig;
 
-	/* add is a cheat, since MIPS has no mov instruction */
-	__asm__ volatile (
-	    "1:"
-	    "ll $3, %1\n"
-	    "add %0, $0, $3\n"
-	    "add $3, $3, %2\n"
-	    "sc $3, %1\n"
-	    "beq $3, 0, 1b"
-	    : "=&r"(orig)
-	    : "m"(*p), "r"(val)
-	    : "memory", "$3"
-		);
+	__asm__ __volatile__ (
+	"	.set	push		\n"
+	"	.set	mips2		\n"
+	"	.set	noreorder	\n"
+	"	.set	noat		\n"
+	"1:	ll	$1, %1		\n"
+	"	addu	%0, $1, %2	\n"
+	"	sc	%0, %1		\n"
+	"	beqz	%0, 1b		\n"
+	"	move	%0, $1		\n"
+	"	.set	pop		\n"
+	: "=&r" (orig), "+R" (*p)
+	: "r" (val)
+	: "memory");
 
 	return (orig);
 }
@@ -44,16 +46,7 @@ isc_atomic_xadd(isc_int32_t *p, int val) {
  */
 static inline void
 isc_atomic_store(isc_int32_t *p, isc_int32_t val) {
-	__asm__ volatile (
-	    "1:"
-	    "ll $3, %0\n"
-	    "add $3, $0, %1\n"
-	    "sc $3, %0\n"
-	    "beq $3, 0, 1b"
-	    :
-	    : "m"(*p), "r"(val)
-	    : "memory", "$3"
-		);
+	*p = val;
 }
 
 /*
@@ -64,20 +57,23 @@ isc_atomic_store(isc_int32_t *p, isc_int32_t val) {
 static inline isc_int32_t
 isc_atomic_cmpxchg(isc_int32_t *p, int cmpval, int val) {
 	isc_int32_t orig;
+	isc_int32_t tmp;
 
-	__asm__ volatile(
-	    "1:"
-	    "ll $3, %1\n"
-	    "add %0, $0, $3\n"
-	    "bne $3, %2, 2f\n"
-	    "add $3, $0, %3\n"
-	    "sc $3, %1\n"
-	    "beq $3, 0, 1b\n"
-	    "2:"
-	    : "=&r"(orig)
-	    : "m"(*p), "r"(cmpval), "r"(val)
-	    : "memory", "$3"
-		);
+	__asm__ __volatile__ (
+	"	.set	push		\n"
+	"	.set	mips2		\n"
+	"	.set	noreorder	\n"
+	"	.set	noat		\n"
+	"1:	ll	$1, %1		\n"
+	"	bne	$1, %3, 2f	\n"
+	"	move	%2, %4		\n"
+	"	sc	%2, %1		\n"
+	"	beqz	%2, 1b		\n"
+	"2:	move	%0, $1		\n"
+	"	.set	pop		\n"
+	: "=&r"(orig), "+R" (*p), "=r" (tmp)
+	: "r"(cmpval), "r"(val)
+	: "memory");
 
 	return (orig);
 }