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Use detected cache line size

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IBM power architecture has L1 cache line size equal to 128.  Take
advantage of that on that architecture, do not force more common value
of 64.  When it is possible to detect higher value, use that value
instead.  Keep the default to be 64.
This commit is contained in:
Petr Menšík
2022-01-25 23:26:27 +01:00
committed by Ondřej Surý
parent bff7dbeef9
commit f00f521e9c
5 changed files with 25 additions and 11 deletions
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4
lib/isc/mem.c
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@@ -459,7 +459,7 @@ mem_create(isc_mem_t **ctxp, unsigned int flags) {
REQUIRE(ctxp != NULL && *ctxp == NULL);
ctx = mallocx(sizeof(*ctx), MALLOCX_ALIGN(ISC_OS_CACHELINE_SIZE));
ctx = mallocx(sizeof(*ctx), MALLOCX_ALIGN(isc_os_cacheline()));
INSIST(ctx != NULL);
*ctx = (isc_mem_t){
@@ -578,7 +578,7 @@ destroy(isc_mem_t *ctx) {
if (ctx->checkfree) {
INSIST(malloced == 0);
}
sdallocx(ctx, sizeof(*ctx), MALLOCX_ALIGN(ISC_OS_CACHELINE_SIZE));
sdallocx(ctx, sizeof(*ctx), MALLOCX_ALIGN(isc_os_cacheline()));
}
void