mirror of
https://gitlab.isc.org/isc-projects/bind9
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161 lines
3.4 KiB
C
161 lines
3.4 KiB
C
/*
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* Copyright (C) 2005 Internet Systems Consortium, Inc. ("ISC")
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES WITH
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* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS. IN NO EVENT SHALL ISC BE LIABLE FOR ANY SPECIAL, DIRECT,
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* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
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* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/* $Id: atomic.h,v 1.4 2007/02/12 00:48:47 marka Exp $ */
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#ifndef ISC_ATOMIC_H
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#define ISC_ATOMIC_H 1
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#include <isc/platform.h>
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#include <isc/types.h>
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/*!\file
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* static inline isc_int32_t
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* isc_atomic_xadd(isc_int32_t *p, isc_int32_t val);
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*
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* This routine atomically increments the value stored in 'p' by 'val', and
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* returns the previous value.
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*
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* static inline void
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* isc_atomic_store(void *p, isc_int32_t val);
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*
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* This routine atomically stores the value 'val' in 'p'.
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*
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* static inline isc_int32_t
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* isc_atomic_cmpxchg(isc_int32_t *p, isc_int32_t cmpval, isc_int32_t val);
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*
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* This routine atomically replaces the value in 'p' with 'val', if the
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* original value is equal to 'cmpval'. The original value is returned in any
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* case.
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*/
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#if defined(_AIX)
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#include <sys/atomic_op.h>
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#define isc_atomic_xadd(p, v) fetch_and_add(p, v)
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#define isc_atomic_store(p, v) _clear_lock(p, v)
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#ifdef __GNUC__
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static inline int
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#else
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static int
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#endif
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isc_atomic_cmpxchg(atomic_p p, int old, int new) {
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int orig = old;
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#ifdef __GNUC__
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asm("ics");
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#else
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__isync();
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#endif
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if (compare_and_swap(p, &orig, new))
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return (old);
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return (orig);
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}
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#elif defined(ISC_PLATFORM_USEGCCASM) || defined(ISC_PLATFORM_USEMACASM)
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static inline isc_int32_t
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isc_atomic_xadd(isc_int32_t *p, isc_int32_t val) {
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isc_int32_t orig;
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__asm__ volatile (
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#ifdef ISC_PLATFORM_USEMACASM
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"1:"
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"lwarx r6, 0, %1\n"
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"mr %0, r6\n"
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"add r6, r6, %2\n"
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"stwcx. r6, 0, %1\n"
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"bne- 1b"
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#else
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"1:"
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"lwarx 6, 0, %1\n"
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"mr %0, 6\n"
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"add 6, 6, %2\n"
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"stwcx. 6, 0, %1\n"
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"bne- 1b"
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#endif
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: "=&r"(orig)
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: "r"(p), "r"(val)
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: "r6", "memory"
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);
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return (orig);
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}
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static inline void
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isc_atomic_store(void *p, isc_int32_t val) {
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__asm__ volatile (
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#ifdef ISC_PLATFORM_USEMACASM
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"1:"
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"lwarx r6, 0, %0\n"
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"lwz r6, %1\n"
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"stwcx. r6, 0, %0\n"
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"bne- 1b"
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#else
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"1:"
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"lwarx 6, 0, %0\n"
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"lwz 6, %1\n"
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"stwcx. 6, 0, %0\n"
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"bne- 1b"
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#endif
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:
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: "r"(p), "m"(val)
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: "r6", "memory"
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);
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}
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static inline isc_int32_t
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isc_atomic_cmpxchg(isc_int32_t *p, isc_int32_t cmpval, isc_int32_t val) {
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isc_int32_t orig;
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__asm__ volatile (
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#ifdef ISC_PLATFORM_USEMACASM
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"1:"
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"lwarx r6, 0, %1\n"
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"mr %0,r6\n"
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"cmpw r6, %2\n"
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"bne 2f\n"
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"mr r6, %3\n"
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"stwcx. r6, 0, %1\n"
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"bne- 1b\n"
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"2:"
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#else
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"1:"
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"lwarx 6, 0, %1\n"
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"mr %0,6\n"
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"cmpw 6, %2\n"
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"bne 2f\n"
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"mr 6, %3\n"
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"stwcx. 6, 0, %1\n"
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"bne- 1b\n"
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"2:"
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#endif
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: "=&r" (orig)
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: "r"(p), "r"(cmpval), "r"(val)
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: "r6", "memory"
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);
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return (orig);
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}
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#else
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#error "unsupported compiler. disable atomic ops by --disable-atomic"
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#endif
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#endif /* ISC_ATOMIC_H */
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