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mirror of https://github.com/checkpoint-restore/criu synced 2025-08-22 09:58:09 +00:00

Run 'make indent' on header files

Acked-by: Mike Rapoport <rppt@linux.ibm.com>
Signed-off-by: Adrian Reber <areber@redhat.com>
This commit is contained in:
Adrian Reber 2021-07-19 07:39:51 +00:00 committed by Andrei Vagin
parent 93dd984ca0
commit 70833bcf29
252 changed files with 4746 additions and 5011 deletions

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@ -1,7 +1,7 @@
#ifndef COMPEL_ARCH_SYSCALL_TYPES_H__
#define COMPEL_ARCH_SYSCALL_TYPES_H__
#define SA_RESTORER 0x04000000
#define SA_RESTORER 0x04000000
typedef void rt_signalfn_t(int, siginfo_t *, void *);
typedef rt_signalfn_t *rt_sighandler_t;
@ -9,20 +9,20 @@ typedef rt_signalfn_t *rt_sighandler_t;
typedef void rt_restorefn_t(void);
typedef rt_restorefn_t *rt_sigrestore_t;
#define _KNSIG 64
#define _NSIG_BPW 64
#define _KNSIG 64
#define _NSIG_BPW 64
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
typedef struct {
unsigned long sig[_KNSIG_WORDS];
} k_rtsigset_t;
typedef struct {
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
} rt_sigaction_t;
#endif /* COMPEL_ARCH_SYSCALL_TYPES_H__ */

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@ -1,3 +1,3 @@
#ifndef __NR_openat
# define __NR_openat 56
#define __NR_openat 56
#endif

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@ -3,8 +3,8 @@
#include "elf64-types.h"
#define __handle_elf handle_elf_aarch64
#define arch_is_machine_supported(e_machine) (e_machine == EM_AARCH64)
#define __handle_elf handle_elf_aarch64
#define arch_is_machine_supported(e_machine) (e_machine == EM_AARCH64)
extern int handle_elf_aarch64(void *mem, size_t size);

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@ -1,4 +1,8 @@
#ifndef __COMPEL_SYSCALL_H__
#define __COMPEL_SYSCALL_H__
#define __NR(syscall, compat) ({ (void)compat; __NR_##syscall; })
#define __NR(syscall, compat) \
({ \
(void)compat; \
__NR_##syscall; \
})
#endif

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@ -1,6 +1,7 @@
#ifndef UAPI_COMPEL_ASM_CPU_H__
#define UAPI_COMPEL_ASM_CPU_H__
typedef struct { } compel_cpuinfo_t;
typedef struct {
} compel_cpuinfo_t;
#endif /* UAPI_COMPEL_ASM_CPU_H__ */

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@ -6,8 +6,8 @@
#include <sys/mman.h>
#include <asm/ptrace.h>
#define SIGMAX 64
#define SIGMAX_OLD 31
#define SIGMAX 64
#define SIGMAX_OLD 31
/*
* Copied from the Linux kernel header arch/arm64/include/uapi/asm/ptrace.h
@ -15,23 +15,27 @@
* A thread ARM CPU context
*/
typedef struct user_pt_regs user_regs_struct_t;
typedef struct user_fpsimd_state user_fpregs_struct_t;
typedef struct user_pt_regs user_regs_struct_t;
typedef struct user_fpsimd_state user_fpregs_struct_t;
#define __compel_arch_fetch_thread_area(tid, th) 0
#define compel_arch_fetch_thread_area(tctl) 0
#define compel_arch_fetch_thread_area(tctl) 0
#define compel_arch_get_tls_task(ctl, tls)
#define compel_arch_get_tls_thread(tctl, tls)
#define REG_RES(r) ((uint64_t)(r).regs[0])
#define REG_IP(r) ((uint64_t)(r).pc)
#define REG_SP(r) ((uint64_t)((r).sp))
#define REG_SYSCALL_NR(r) ((uint64_t)(r).regs[8])
#define REG_RES(r) ((uint64_t)(r).regs[0])
#define REG_IP(r) ((uint64_t)(r).pc)
#define REG_SP(r) ((uint64_t)((r).sp))
#define REG_SYSCALL_NR(r) ((uint64_t)(r).regs[8])
#define user_regs_native(pregs) true
#define user_regs_native(pregs) true
#define ARCH_SI_TRAP TRAP_BRKPT
#define ARCH_SI_TRAP TRAP_BRKPT
#define __NR(syscall, compat) ({ (void)compat; __NR_##syscall; })
#define __NR(syscall, compat) \
({ \
(void)compat; \
__NR_##syscall; \
})
#endif /* UAPI_COMPEL_ASM_TYPES_H__ */

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@ -8,30 +8,31 @@
/* Copied from the kernel header arch/arm64/include/uapi/asm/sigcontext.h */
#define FPSIMD_MAGIC 0x46508001
#define FPSIMD_MAGIC 0x46508001
typedef struct fpsimd_context fpu_state_t;
typedef struct fpsimd_context fpu_state_t;
struct aux_context {
struct fpsimd_context fpsimd;
struct fpsimd_context fpsimd;
/* additional context to be added before "end" */
struct _aarch64_ctx end;
struct _aarch64_ctx end;
};
// XXX: the idetifier rt_sigcontext is expected to be struct by the CRIU code
#define rt_sigcontext sigcontext
#define rt_sigcontext sigcontext
#include <compel/sigframe-common.h>
/* Copied from the kernel source arch/arm64/kernel/signal.c */
struct rt_sigframe {
siginfo_t info;
ucontext_t uc;
uint64_t fp;
uint64_t lr;
siginfo_t info;
ucontext_t uc;
uint64_t fp;
uint64_t lr;
};
/* clang-format off */
#define ARCH_RT_SIGRETURN(new_sp, rt_sigframe) \
asm volatile( \
"mov sp, %0 \n" \
@ -40,30 +41,29 @@ struct rt_sigframe {
: \
: "r"(new_sp) \
: "x8", "memory")
/* clang-format on */
/* cr_sigcontext is copied from arch/arm64/include/uapi/asm/sigcontext.h */
struct cr_sigcontext {
__u64 fault_address;
/* AArch64 registers */
__u64 regs[31];
__u64 sp;
__u64 pc;
__u64 pstate;
/* 4K reserved for FP/SIMD state and future expansion */
__u8 __reserved[4096] __attribute__((__aligned__(16)));
__u64 fault_address;
/* AArch64 registers */
__u64 regs[31];
__u64 sp;
__u64 pc;
__u64 pstate;
/* 4K reserved for FP/SIMD state and future expansion */
__u8 __reserved[4096] __attribute__((__aligned__(16)));
};
#define RT_SIGFRAME_UC(rt_sigframe) (&rt_sigframe->uc)
#define RT_SIGFRAME_REGIP(rt_sigframe) ((long unsigned int)(rt_sigframe)->uc.uc_mcontext.pc)
#define RT_SIGFRAME_HAS_FPU(rt_sigframe) (1)
#define RT_SIGFRAME_SIGCONTEXT(rt_sigframe) ((struct cr_sigcontext *)&(rt_sigframe)->uc.uc_mcontext)
#define RT_SIGFRAME_AUX_CONTEXT(rt_sigframe) ((struct aux_context*)&(RT_SIGFRAME_SIGCONTEXT(rt_sigframe)->__reserved))
#define RT_SIGFRAME_FPU(rt_sigframe) (&RT_SIGFRAME_AUX_CONTEXT(rt_sigframe)->fpsimd)
#define RT_SIGFRAME_OFFSET(rt_sigframe) 0
#define RT_SIGFRAME_UC(rt_sigframe) (&rt_sigframe->uc)
#define RT_SIGFRAME_REGIP(rt_sigframe) ((long unsigned int)(rt_sigframe)->uc.uc_mcontext.pc)
#define RT_SIGFRAME_HAS_FPU(rt_sigframe) (1)
#define RT_SIGFRAME_SIGCONTEXT(rt_sigframe) ((struct cr_sigcontext *)&(rt_sigframe)->uc.uc_mcontext)
#define RT_SIGFRAME_AUX_CONTEXT(rt_sigframe) ((struct aux_context *)&(RT_SIGFRAME_SIGCONTEXT(rt_sigframe)->__reserved))
#define RT_SIGFRAME_FPU(rt_sigframe) (&RT_SIGFRAME_AUX_CONTEXT(rt_sigframe)->fpsimd)
#define RT_SIGFRAME_OFFSET(rt_sigframe) 0
#define rt_sigframe_erase_sigset(sigframe) \
memset(&sigframe->uc.uc_sigmask, 0, sizeof(k_rtsigset_t))
#define rt_sigframe_copy_sigset(sigframe, from) \
memcpy(&sigframe->uc.uc_sigmask, from, sizeof(k_rtsigset_t))
#define rt_sigframe_erase_sigset(sigframe) memset(&sigframe->uc.uc_sigmask, 0, sizeof(k_rtsigset_t))
#define rt_sigframe_copy_sigset(sigframe, from) memcpy(&sigframe->uc.uc_sigmask, from, sizeof(k_rtsigset_t))
#endif /* UAPI_COMPEL_ASM_SIGFRAME_H__ */

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@ -1,7 +1,7 @@
#ifndef COMPEL_ARCH_SYSCALL_TYPES_H__
#define COMPEL_ARCH_SYSCALL_TYPES_H__
#define SA_RESTORER 0x04000000
#define SA_RESTORER 0x04000000
typedef void rt_signalfn_t(int, siginfo_t *, void *);
typedef rt_signalfn_t *rt_sighandler_t;
@ -9,20 +9,20 @@ typedef rt_signalfn_t *rt_sighandler_t;
typedef void rt_restorefn_t(void);
typedef rt_restorefn_t *rt_sigrestore_t;
#define _KNSIG 64
#define _NSIG_BPW 32
#define _KNSIG 64
#define _NSIG_BPW 32
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
typedef struct {
unsigned long sig[_KNSIG_WORDS];
} k_rtsigset_t;
typedef struct {
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
} rt_sigaction_t;
#endif /* COMPEL_ARCH_SYSCALL_TYPES_H__ */

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@ -1,27 +1,27 @@
#ifndef __NR_mmap2
# define __NR_mmap2 192
#define __NR_mmap2 192
#endif
#ifndef __ARM_NR_BASE
# define __ARM_NR_BASE 0x0f0000
#define __ARM_NR_BASE 0x0f0000
#endif
#ifndef __ARM_NR_breakpoint
# define __ARM_NR_breakpoint (__ARM_NR_BASE+1)
#define __ARM_NR_breakpoint (__ARM_NR_BASE + 1)
#endif
#ifndef __ARM_NR_cacheflush
# define __ARM_NR_cacheflush (__ARM_NR_BASE+2)
#define __ARM_NR_cacheflush (__ARM_NR_BASE + 2)
#endif
#ifndef __ARM_NR_usr26
# define __ARM_NR_usr26 (__ARM_NR_BASE+3)
#define __ARM_NR_usr26 (__ARM_NR_BASE + 3)
#endif
#ifndef __ARM_NR_usr32
# define __ARM_NR_usr32 (__ARM_NR_BASE+4)
#define __ARM_NR_usr32 (__ARM_NR_BASE + 4)
#endif
#ifndef __ARM_NR_set_tls
# define __ARM_NR_set_tls (__ARM_NR_BASE+5)
#define __ARM_NR_set_tls (__ARM_NR_BASE + 5)
#endif

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@ -3,8 +3,8 @@
#include "elf32-types.h"
#define __handle_elf handle_elf_arm
#define arch_is_machine_supported(e_machine) (e_machine == EM_ARM)
#define __handle_elf handle_elf_arm
#define arch_is_machine_supported(e_machine) (e_machine == EM_ARM)
extern int handle_elf_arm(void *mem, size_t size);

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@ -1,4 +1,8 @@
#ifndef __COMPEL_SYSCALL_H__
#define __COMPEL_SYSCALL_H__
#define __NR(syscall, compat) ({ (void)compat; __NR_##syscall; })
#define __NR(syscall, compat) \
({ \
(void)compat; \
__NR_##syscall; \
})
#endif

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@ -1,6 +1,7 @@
#ifndef UAPI_COMPEL_ASM_CPU_H__
#define UAPI_COMPEL_ASM_CPU_H__
typedef struct { } compel_cpuinfo_t;
typedef struct {
} compel_cpuinfo_t;
#endif /* UAPI_COMPEL_ASM_CPU_H__ */

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@ -4,8 +4,8 @@
#include <stdint.h>
#include <sys/mman.h>
#define SIGMAX 64
#define SIGMAX_OLD 31
#define SIGMAX 64
#define SIGMAX_OLD 31
/*
* Copied from the Linux kernel header arch/arm/include/asm/ptrace.h
@ -14,58 +14,61 @@
*/
typedef struct {
long uregs[18];
long uregs[18];
} user_regs_struct_t;
#define __compel_arch_fetch_thread_area(tid, th) 0
#define compel_arch_fetch_thread_area(tctl) 0
#define compel_arch_fetch_thread_area(tctl) 0
#define compel_arch_get_tls_task(ctl, tls)
#define compel_arch_get_tls_thread(tctl, tls)
typedef struct user_vfp user_fpregs_struct_t;
#define ARM_cpsr uregs[16]
#define ARM_pc uregs[15]
#define ARM_lr uregs[14]
#define ARM_sp uregs[13]
#define ARM_ip uregs[12]
#define ARM_fp uregs[11]
#define ARM_r10 uregs[10]
#define ARM_r9 uregs[9]
#define ARM_r8 uregs[8]
#define ARM_r7 uregs[7]
#define ARM_r6 uregs[6]
#define ARM_r5 uregs[5]
#define ARM_r4 uregs[4]
#define ARM_r3 uregs[3]
#define ARM_r2 uregs[2]
#define ARM_r1 uregs[1]
#define ARM_r0 uregs[0]
#define ARM_ORIG_r0 uregs[17]
typedef struct user_vfp user_fpregs_struct_t;
#define ARM_cpsr uregs[16]
#define ARM_pc uregs[15]
#define ARM_lr uregs[14]
#define ARM_sp uregs[13]
#define ARM_ip uregs[12]
#define ARM_fp uregs[11]
#define ARM_r10 uregs[10]
#define ARM_r9 uregs[9]
#define ARM_r8 uregs[8]
#define ARM_r7 uregs[7]
#define ARM_r6 uregs[6]
#define ARM_r5 uregs[5]
#define ARM_r4 uregs[4]
#define ARM_r3 uregs[3]
#define ARM_r2 uregs[2]
#define ARM_r1 uregs[1]
#define ARM_r0 uregs[0]
#define ARM_ORIG_r0 uregs[17]
/* Copied from arch/arm/include/asm/user.h */
struct user_vfp {
unsigned long long fpregs[32];
unsigned long fpscr;
unsigned long long fpregs[32];
unsigned long fpscr;
};
struct user_vfp_exc {
unsigned long fpexc;
unsigned long fpinst;
unsigned long fpinst2;
unsigned long fpexc;
unsigned long fpinst;
unsigned long fpinst2;
};
#define REG_RES(regs) ((regs).ARM_r0)
#define REG_IP(regs) ((regs).ARM_pc)
#define REG_SP(regs) ((regs).ARM_sp)
#define REG_SYSCALL_NR(regs) ((regs).ARM_r7)
#define REG_RES(regs) ((regs).ARM_r0)
#define REG_IP(regs) ((regs).ARM_pc)
#define REG_SP(regs) ((regs).ARM_sp)
#define REG_SYSCALL_NR(regs) ((regs).ARM_r7)
#define user_regs_native(pregs) true
#define user_regs_native(pregs) true
#define ARCH_SI_TRAP TRAP_BRKPT
#define ARCH_SI_TRAP TRAP_BRKPT
#define __NR(syscall, compat) ({ (void)compat; __NR_##syscall; })
#define __NR(syscall, compat) \
({ \
(void)compat; \
__NR_##syscall; \
})
#endif /* UAPI_COMPEL_ASM_TYPES_H__ */

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@ -6,37 +6,37 @@
/*
* PSR bits
*/
#define USR26_MODE 0x00000000
#define FIQ26_MODE 0x00000001
#define IRQ26_MODE 0x00000002
#define SVC26_MODE 0x00000003
#define USR_MODE 0x00000010
#define FIQ_MODE 0x00000011
#define IRQ_MODE 0x00000012
#define SVC_MODE 0x00000013
#define ABT_MODE 0x00000017
#define UND_MODE 0x0000001b
#define SYSTEM_MODE 0x0000001f
#define MODE32_BIT 0x00000010
#define MODE_MASK 0x0000001f
#define PSR_T_BIT 0x00000020
#define PSR_F_BIT 0x00000040
#define PSR_I_BIT 0x00000080
#define PSR_A_BIT 0x00000100
#define PSR_E_BIT 0x00000200
#define PSR_J_BIT 0x01000000
#define PSR_Q_BIT 0x08000000
#define PSR_V_BIT 0x10000000
#define PSR_C_BIT 0x20000000
#define PSR_Z_BIT 0x40000000
#define PSR_N_BIT 0x80000000
#define USR26_MODE 0x00000000
#define FIQ26_MODE 0x00000001
#define IRQ26_MODE 0x00000002
#define SVC26_MODE 0x00000003
#define USR_MODE 0x00000010
#define FIQ_MODE 0x00000011
#define IRQ_MODE 0x00000012
#define SVC_MODE 0x00000013
#define ABT_MODE 0x00000017
#define UND_MODE 0x0000001b
#define SYSTEM_MODE 0x0000001f
#define MODE32_BIT 0x00000010
#define MODE_MASK 0x0000001f
#define PSR_T_BIT 0x00000020
#define PSR_F_BIT 0x00000040
#define PSR_I_BIT 0x00000080
#define PSR_A_BIT 0x00000100
#define PSR_E_BIT 0x00000200
#define PSR_J_BIT 0x01000000
#define PSR_Q_BIT 0x08000000
#define PSR_V_BIT 0x10000000
#define PSR_C_BIT 0x20000000
#define PSR_Z_BIT 0x40000000
#define PSR_N_BIT 0x80000000
/*
* Groups of PSR bits
*/
#define PSR_f 0xff000000 /* Flags */
#define PSR_s 0x00ff0000 /* Status */
#define PSR_x 0x0000ff00 /* Extension */
#define PSR_c 0x000000ff /* Control */
#define PSR_f 0xff000000 /* Flags */
#define PSR_s 0x00ff0000 /* Status */
#define PSR_x 0x0000ff00 /* Extension */
#define PSR_c 0x000000ff /* Control */
#endif

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@ -6,42 +6,42 @@
/* Copied from the Linux kernel header arch/arm/include/asm/sigcontext.h */
struct rt_sigcontext {
unsigned long trap_no;
unsigned long error_code;
unsigned long oldmask;
unsigned long arm_r0;
unsigned long arm_r1;
unsigned long arm_r2;
unsigned long arm_r3;
unsigned long arm_r4;
unsigned long arm_r5;
unsigned long arm_r6;
unsigned long arm_r7;
unsigned long arm_r8;
unsigned long arm_r9;
unsigned long arm_r10;
unsigned long arm_fp;
unsigned long arm_ip;
unsigned long arm_sp;
unsigned long arm_lr;
unsigned long arm_pc;
unsigned long arm_cpsr;
unsigned long fault_address;
unsigned long trap_no;
unsigned long error_code;
unsigned long oldmask;
unsigned long arm_r0;
unsigned long arm_r1;
unsigned long arm_r2;
unsigned long arm_r3;
unsigned long arm_r4;
unsigned long arm_r5;
unsigned long arm_r6;
unsigned long arm_r7;
unsigned long arm_r8;
unsigned long arm_r9;
unsigned long arm_r10;
unsigned long arm_fp;
unsigned long arm_ip;
unsigned long arm_sp;
unsigned long arm_lr;
unsigned long arm_pc;
unsigned long arm_cpsr;
unsigned long fault_address;
};
/* Copied from the Linux kernel header arch/arm/include/asm/ucontext.h */
#define VFP_MAGIC 0x56465001
#define VFP_STORAGE_SIZE sizeof(struct vfp_sigframe)
#define VFP_MAGIC 0x56465001
#define VFP_STORAGE_SIZE sizeof(struct vfp_sigframe)
struct vfp_sigframe {
unsigned long magic;
unsigned long size;
struct user_vfp ufp;
struct user_vfp_exc ufp_exc;
unsigned long magic;
unsigned long size;
struct user_vfp ufp;
struct user_vfp_exc ufp_exc;
};
typedef struct vfp_sigframe fpu_state_t;
typedef struct vfp_sigframe fpu_state_t;
struct aux_sigframe {
/*
@ -49,23 +49,23 @@ struct aux_sigframe {
struct iwmmxt_sigframe iwmmxt;
*/
struct vfp_sigframe vfp;
unsigned long end_magic;
struct vfp_sigframe vfp;
unsigned long end_magic;
} __attribute__((aligned(8)));
#include <compel/sigframe-common.h>
struct sigframe {
struct rt_ucontext uc;
unsigned long retcode[2];
struct rt_ucontext uc;
unsigned long retcode[2];
};
struct rt_sigframe {
struct rt_siginfo info;
struct sigframe sig;
struct rt_siginfo info;
struct sigframe sig;
};
/* clang-format off */
#define ARCH_RT_SIGRETURN(new_sp, rt_sigframe) \
asm volatile( \
"mov sp, %0 \n" \
@ -74,17 +74,16 @@ struct rt_sigframe {
: \
: "r"(new_sp) \
: "memory")
/* clang-format on */
#define RT_SIGFRAME_UC(rt_sigframe) (&rt_sigframe->sig.uc)
#define RT_SIGFRAME_REGIP(rt_sigframe) (rt_sigframe)->sig.uc.uc_mcontext.arm_ip
#define RT_SIGFRAME_HAS_FPU(rt_sigframe) 1
#define RT_SIGFRAME_AUX_SIGFRAME(rt_sigframe) ((struct aux_sigframe *)&(rt_sigframe)->sig.uc.uc_regspace)
#define RT_SIGFRAME_FPU(rt_sigframe) (&RT_SIGFRAME_AUX_SIGFRAME(rt_sigframe)->vfp)
#define RT_SIGFRAME_OFFSET(rt_sigframe) 0
#define RT_SIGFRAME_UC(rt_sigframe) (&rt_sigframe->sig.uc)
#define RT_SIGFRAME_REGIP(rt_sigframe) (rt_sigframe)->sig.uc.uc_mcontext.arm_ip
#define RT_SIGFRAME_HAS_FPU(rt_sigframe) 1
#define RT_SIGFRAME_AUX_SIGFRAME(rt_sigframe) ((struct aux_sigframe *)&(rt_sigframe)->sig.uc.uc_regspace)
#define RT_SIGFRAME_FPU(rt_sigframe) (&RT_SIGFRAME_AUX_SIGFRAME(rt_sigframe)->vfp)
#define RT_SIGFRAME_OFFSET(rt_sigframe) 0
#define rt_sigframe_erase_sigset(sigframe) \
memset(&sigframe->sig.uc.uc_sigmask, 0, sizeof(k_rtsigset_t))
#define rt_sigframe_copy_sigset(sigframe, from) \
memcpy(&sigframe->sig.uc.uc_sigmask, from, sizeof(k_rtsigset_t))
#define rt_sigframe_erase_sigset(sigframe) memset(&sigframe->sig.uc.uc_sigmask, 0, sizeof(k_rtsigset_t))
#define rt_sigframe_copy_sigset(sigframe, from) memcpy(&sigframe->sig.uc.uc_sigmask, from, sizeof(k_rtsigset_t))
#endif /* UAPI_COMPEL_ASM_SIGFRAME_H__ */

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@ -9,17 +9,16 @@
#include <errno.h>
#define sys_recv(sockfd, ubuf, size, flags) \
sys_recvfrom(sockfd, ubuf, size, flags, NULL, NULL)
#define sys_recv(sockfd, ubuf, size, flags) sys_recvfrom(sockfd, ubuf, size, flags, NULL, NULL)
typedef struct prologue_init_args {
struct sockaddr_un ctl_sock_addr;
unsigned int ctl_sock_addr_len;
struct sockaddr_un ctl_sock_addr;
unsigned int ctl_sock_addr_len;
unsigned int arg_s;
void *arg_p;
unsigned int arg_s;
void *arg_p;
void *sigframe;
void *sigframe;
} prologue_init_args_t;
#endif /* __ASSEMBLY__ */
@ -29,8 +28,8 @@ typedef struct prologue_init_args {
*
* FIXME It is rather should be taken from sigframe header.
*/
#define PROLOGUE_SGFRAME_SIZE 4096
#define PROLOGUE_SGFRAME_SIZE 4096
#define PROLOGUE_INIT_ARGS_SIZE 1024
#define PROLOGUE_INIT_ARGS_SIZE 1024
#endif /* __ASM_PROLOGUE_H__ */

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@ -8,13 +8,13 @@ typedef rt_signalfn_t *rt_sighandler_t;
typedef void rt_restorefn_t(void);
typedef rt_restorefn_t *rt_sigrestore_t;
#define SA_RESTORER 0x04000000
#define SA_RESTORER 0x04000000
/** refer to linux-3.10/arch/mips/include/uapi/asm/signal.h*/
#define _KNSIG 128
#define _NSIG_BPW 64
#define _KNSIG 128
#define _NSIG_BPW 64
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
/*
* Note: as k_rtsigset_t is the same size for 32-bit and 64-bit,
@ -23,14 +23,14 @@ typedef rt_restorefn_t *rt_sigrestore_t;
*/
typedef struct {
uint64_t sig[_KNSIG_WORDS];
uint64_t sig[_KNSIG_WORDS];
} k_rtsigset_t;
typedef struct {
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
} rt_sigaction_t;
#endif /* COMPEL_ARCH_SYSCALL_TYPES_H__ */

View File

@ -3,6 +3,6 @@
#include "elf64-types.h"
#define arch_is_machine_supported(e_machine) (e_machine == EM_MIPS)
#define arch_is_machine_supported(e_machine) (e_machine == EM_MIPS)
#endif /* COMPEL_HANDLE_ELF_H__ */

View File

@ -28,39 +28,27 @@ struct La_mips_32_retval;
struct La_mips_64_regs;
struct La_mips_64_retval;
#define ARCH_PLTENTER_MEMBERS \
Elf32_Addr (*mips_o32_gnu_pltenter) (Elf32_Sym *, unsigned int, \
uintptr_t *, uintptr_t *, \
struct La_mips_32_regs *, \
unsigned int *, const char *name, \
long int *framesizep); \
Elf32_Addr (*mips_n32_gnu_pltenter) (Elf32_Sym *, unsigned int, \
uintptr_t *, uintptr_t *, \
struct La_mips_64_regs *, \
unsigned int *, const char *name, \
long int *framesizep); \
Elf64_Addr (*mips_n64_gnu_pltenter) (Elf64_Sym *, unsigned int, \
uintptr_t *, uintptr_t *, \
struct La_mips_64_regs *, \
unsigned int *, const char *name, \
long int *framesizep);
#define ARCH_PLTENTER_MEMBERS \
Elf32_Addr (*mips_o32_gnu_pltenter)(Elf32_Sym *, unsigned int, uintptr_t *, uintptr_t *, \
struct La_mips_32_regs *, unsigned int *, const char *name, \
long int *framesizep); \
Elf32_Addr (*mips_n32_gnu_pltenter)(Elf32_Sym *, unsigned int, uintptr_t *, uintptr_t *, \
struct La_mips_64_regs *, unsigned int *, const char *name, \
long int *framesizep); \
Elf64_Addr (*mips_n64_gnu_pltenter)(Elf64_Sym *, unsigned int, uintptr_t *, uintptr_t *, \
struct La_mips_64_regs *, unsigned int *, const char *name, \
long int *framesizep);
#define ARCH_PLTEXIT_MEMBERS \
unsigned int (*mips_o32_gnu_pltexit) (Elf32_Sym *, unsigned int, \
uintptr_t *, uintptr_t *, \
const struct La_mips_32_regs *, \
struct La_mips_32_retval *, \
const char *); \
unsigned int (*mips_n32_gnu_pltexit) (Elf32_Sym *, unsigned int, \
uintptr_t *, uintptr_t *, \
const struct La_mips_64_regs *, \
struct La_mips_64_retval *, \
const char *); \
unsigned int (*mips_n64_gnu_pltexit) (Elf64_Sym *, unsigned int, \
uintptr_t *, uintptr_t *, \
const struct La_mips_64_regs *, \
struct La_mips_64_retval *, \
const char *);
#define ARCH_PLTEXIT_MEMBERS \
unsigned int (*mips_o32_gnu_pltexit)(Elf32_Sym *, unsigned int, uintptr_t *, uintptr_t *, \
const struct La_mips_32_regs *, struct La_mips_32_retval *, \
const char *); \
unsigned int (*mips_n32_gnu_pltexit)(Elf32_Sym *, unsigned int, uintptr_t *, uintptr_t *, \
const struct La_mips_64_regs *, struct La_mips_64_retval *, \
const char *); \
unsigned int (*mips_n64_gnu_pltexit)(Elf64_Sym *, unsigned int, uintptr_t *, uintptr_t *, \
const struct La_mips_64_regs *, struct La_mips_64_retval *, \
const char *);
/* The MIPS ABI specifies that the dynamic section has to be read-only. */
@ -80,77 +68,63 @@ struct La_mips_64_retval;
/* An entry in a 64 bit SHT_REL section. */
typedef struct
{
Elf32_Word r_sym; /* Symbol index */
unsigned char r_ssym; /* Special symbol for 2nd relocation */
unsigned char r_type3; /* 3rd relocation type */
unsigned char r_type2; /* 2nd relocation type */
unsigned char r_type1; /* 1st relocation type */
typedef struct {
Elf32_Word r_sym; /* Symbol index */
unsigned char r_ssym; /* Special symbol for 2nd relocation */
unsigned char r_type3; /* 3rd relocation type */
unsigned char r_type2; /* 2nd relocation type */
unsigned char r_type1; /* 1st relocation type */
} _Elf64_Mips_R_Info;
typedef union
{
Elf64_Xword r_info_number;
typedef union {
Elf64_Xword r_info_number;
_Elf64_Mips_R_Info r_info_fields;
} _Elf64_Mips_R_Info_union;
typedef struct
{
Elf64_Addr r_offset; /* Address */
_Elf64_Mips_R_Info_union r_info; /* Relocation type and symbol index */
typedef struct {
Elf64_Addr r_offset; /* Address */
_Elf64_Mips_R_Info_union r_info; /* Relocation type and symbol index */
} Elf64_Mips_Rel;
typedef struct
{
Elf64_Addr r_offset; /* Address */
_Elf64_Mips_R_Info_union r_info; /* Relocation type and symbol index */
Elf64_Sxword r_addend; /* Addend */
typedef struct {
Elf64_Addr r_offset; /* Address */
_Elf64_Mips_R_Info_union r_info; /* Relocation type and symbol index */
Elf64_Sxword r_addend; /* Addend */
} Elf64_Mips_Rela;
#define ELF64_MIPS_R_SYM(i) \
((__extension__ (_Elf64_Mips_R_Info_union)(i)).r_info_fields.r_sym)
#define ELF64_MIPS_R_SYM(i) ((__extension__(_Elf64_Mips_R_Info_union)(i)).r_info_fields.r_sym)
#define ELF64_MIPS_R_TYPE(i) \
(((_Elf64_Mips_R_Info_union)(i)).r_info_fields.r_type1 \
| ((Elf32_Word)(__extension__ (_Elf64_Mips_R_Info_union)(i) \
).r_info_fields.r_type2 << 8) \
| ((Elf32_Word)(__extension__ (_Elf64_Mips_R_Info_union)(i) \
).r_info_fields.r_type3 << 16) \
| ((Elf32_Word)(__extension__ (_Elf64_Mips_R_Info_union)(i) \
).r_info_fields.r_ssym << 24))
#define ELF64_MIPS_R_TYPE(i) \
(((_Elf64_Mips_R_Info_union)(i)).r_info_fields.r_type1 | \
((Elf32_Word)(__extension__(_Elf64_Mips_R_Info_union)(i)).r_info_fields.r_type2 << 8) | \
((Elf32_Word)(__extension__(_Elf64_Mips_R_Info_union)(i)).r_info_fields.r_type3 << 16) | \
((Elf32_Word)(__extension__(_Elf64_Mips_R_Info_union)(i)).r_info_fields.r_ssym << 24))
#define ELF64_MIPS_R_INFO(sym, type) \
(__extension__ (_Elf64_Mips_R_Info_union) \
(__extension__ (_Elf64_Mips_R_Info) \
{ (sym), ELF64_MIPS_R_SSYM (type), \
ELF64_MIPS_R_TYPE3 (type), \
ELF64_MIPS_R_TYPE2 (type), \
ELF64_MIPS_R_TYPE1 (type) \
}).r_info_number)
#define ELF64_MIPS_R_INFO(sym, type) \
(__extension__(_Elf64_Mips_R_Info_union)( \
__extension__(_Elf64_Mips_R_Info){ (sym), ELF64_MIPS_R_SSYM(type), ELF64_MIPS_R_TYPE3(type), \
ELF64_MIPS_R_TYPE2(type), ELF64_MIPS_R_TYPE1(type) }) \
.r_info_number)
/*
* These macros decompose the value returned by ELF64_MIPS_R_TYPE, and
* compose it back into a value that it can be used as an argument to
* ELF64_MIPS_R_INFO.
*/
#define ELF64_MIPS_R_SSYM(i) (((i) >> 24) & 0xff)
#define ELF64_MIPS_R_SSYM(i) (((i) >> 24) & 0xff)
#define ELF64_MIPS_R_TYPE3(i) (((i) >> 16) & 0xff)
#define ELF64_MIPS_R_TYPE2(i) (((i) >> 8) & 0xff)
#define ELF64_MIPS_R_TYPE1(i) ((i) & 0xff)
#define ELF64_MIPS_R_TYPE1(i) ((i)&0xff)
#define ELF64_MIPS_R_TYPEENC(type1, type2, type3, ssym) \
((type1) \
| ((Elf32_Word)(type2) << 8) \
| ((Elf32_Word)(type3) << 16) \
| ((Elf32_Word)(ssym) << 24))
((type1) | ((Elf32_Word)(type2) << 8) | ((Elf32_Word)(type3) << 16) | ((Elf32_Word)(ssym) << 24))
#undef ELF64_R_SYM
#define ELF64_R_SYM(i) ELF64_MIPS_R_SYM (i)
#define ELF64_R_SYM(i) ELF64_MIPS_R_SYM(i)
#undef ELF64_R_TYPE
/*fixme*/
#define ELF64_R_TYPE(i) (ELF64_MIPS_R_TYPE (i) & 0x00ff)
#define ELF64_R_TYPE(i) (ELF64_MIPS_R_TYPE(i) & 0x00ff)
#undef ELF64_R_INFO
#define ELF64_R_INFO(sym, type) ELF64_MIPS_R_INFO ((sym), (type))
#define ELF64_R_INFO(sym, type) ELF64_MIPS_R_INFO((sym), (type))
#endif

View File

@ -2,6 +2,6 @@
#define __COMPEL_SYSCALL_H__
#ifndef SIGSTKFLT
#define SIGSTKFLT 16
#define SIGSTKFLT 16
#endif
#endif

View File

@ -1,5 +1,6 @@
#ifndef __CR_ASM_CPU_H__
#define __CR_ASM_CPU_H__
typedef struct { } compel_cpuinfo_t;
typedef struct {
} compel_cpuinfo_t;
#endif /* __CR_ASM_CPU_H__ */

View File

@ -6,8 +6,8 @@
#include <signal.h>
#include <compel/plugins/std/asm/syscall-types.h>
#include <linux/types.h>
#define SIGMAX 64
#define SIGMAX_OLD 31
#define SIGMAX 64
#define SIGMAX_OLD 31
/*
* Copied from the Linux kernel header arch/mips/include/asm/ptrace.h
@ -35,35 +35,33 @@ typedef struct {
__u32 fpu_fcr31;
__u32 fpu_id;
} user_fpregs_struct_t;
#define MIPS_a0 regs[4] //arguments a0-a3
#define MIPS_t0 regs[8] //temporaries t0-t7
#define MIPS_v0 regs[2]
#define MIPS_v1 regs[3]
#define MIPS_sp regs[29]
#define MIPS_ra regs[31]
#define MIPS_a0 regs[4] //arguments a0-a3
#define MIPS_t0 regs[8] //temporaries t0-t7
#define MIPS_v0 regs[2]
#define MIPS_v1 regs[3]
#define MIPS_sp regs[29]
#define MIPS_ra regs[31]
#define NATIVE_MAGIC 0x0A
#define COMPAT_MAGIC 0x0C
#define NATIVE_MAGIC 0x0A
#define COMPAT_MAGIC 0x0C
static inline bool user_regs_native(user_regs_struct_t *pregs)
{
return true;
}
#define __compel_arch_fetch_thread_area(tid, th) 0
#define compel_arch_fetch_thread_area(tctl) 0
#define compel_arch_fetch_thread_area(tctl) 0
#define compel_arch_get_tls_task(ctl, tls)
#define compel_arch_get_tls_thread(tctl, tls)
#define REG_RES(regs) ((regs).MIPS_v0)
#define REG_IP(regs) ((regs).cp0_epc)
#define REG_SP(regs) ((regs).MIPS_sp)
#define REG_SYSCALL_NR(regs) ((regs).MIPS_v0)
#define REG_RES(regs) ((regs).MIPS_v0)
#define REG_IP(regs) ((regs).cp0_epc)
#define REG_SP(regs) ((regs).MIPS_sp)
#define REG_SYSCALL_NR(regs) ((regs).MIPS_v0)
//#define __NR(syscall, compat) ((compat) ? __NR32_##syscall : __NR_##syscall)
#define __NR(syscall, compat) __NR_##syscall
#define __NR(syscall, compat) __NR_##syscall
#endif /* UAPI_COMPEL_ASM_TYPES_H__ */

View File

@ -11,13 +11,12 @@
#define u32 __u32
/* sigcontext defined in /usr/include/asm/sigcontext.h*/
#define rt_sigcontext sigcontext
#define rt_sigcontext sigcontext
#include <compel/sigframe-common.h>
/* refer to linux-3.10/include/uapi/asm-generic/ucontext.h */
struct k_ucontext{
struct k_ucontext {
unsigned long uc_flags;
struct k_ucontext *uc_link;
stack_t uc_stack;
@ -27,23 +26,21 @@ struct k_ucontext{
/* Copy from the kernel source arch/mips/kernel/signal.c */
struct rt_sigframe {
u32 rs_ass[4]; /* argument save space for o32 */
u32 rs_pad[2]; /* Was: signal trampoline */
u32 rs_ass[4]; /* argument save space for o32 */
u32 rs_pad[2]; /* Was: signal trampoline */
siginfo_t rs_info;
struct k_ucontext rs_uc;
};
#define RT_SIGFRAME_UC(rt_sigframe) (&rt_sigframe->rs_uc)
#define RT_SIGFRAME_UC_SIGMASK(rt_sigframe) ((k_rtsigset_t *)(void *)&rt_sigframe->rs_uc.uc_sigmask)
#define RT_SIGFRAME_REGIP(rt_sigframe) ((long unsigned int)0x00)
#define RT_SIGFRAME_UC(rt_sigframe) (&rt_sigframe->rs_uc)
#define RT_SIGFRAME_UC_SIGMASK(rt_sigframe) ((k_rtsigset_t *)(void *)&rt_sigframe->rs_uc.uc_sigmask)
#define RT_SIGFRAME_REGIP(rt_sigframe) ((long unsigned int)0x00)
#define RT_SIGFRAME_FPU(rt_sigframe)
#define RT_SIGFRAME_HAS_FPU(rt_sigframe) 1
#define RT_SIGFRAME_OFFSET(rt_sigframe) 0
#define RT_SIGFRAME_OFFSET(rt_sigframe) 0
/* clang-format off */
#define ARCH_RT_SIGRETURN(new_sp, rt_sigframe) \
asm volatile( \
"move $29, %0 \n" \
@ -52,12 +49,10 @@ struct rt_sigframe {
: \
: "r"(new_sp) \
: "$2","memory")
/* clang-format on */
int sigreturn_prep_fpu_frame(struct rt_sigframe *sigframe,
struct rt_sigframe *rsigframe);
int sigreturn_prep_fpu_frame(struct rt_sigframe *sigframe, struct rt_sigframe *rsigframe);
#define rt_sigframe_erase_sigset(sigframe) \
memset(&sigframe->rs_uc.uc_sigmask, 0, sizeof(k_rtsigset_t))
#define rt_sigframe_copy_sigset(sigframe, from) \
memcpy(&sigframe->rs_uc.uc_sigmask, from, sizeof(k_rtsigset_t))
#define rt_sigframe_erase_sigset(sigframe) memset(&sigframe->rs_uc.uc_sigmask, 0, sizeof(k_rtsigset_t))
#define rt_sigframe_copy_sigset(sigframe, from) memcpy(&sigframe->rs_uc.uc_sigmask, from, sizeof(k_rtsigset_t))
#endif /* UAPI_COMPEL_ASM_SIGFRAME_H__ */

View File

@ -9,8 +9,7 @@
#ifndef _UAPI_ASM_SIGINFO_H
#define _UAPI_ASM_SIGINFO_H
#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2 * sizeof(int))
#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ... */
#define HAVE_ARCH_SIGINFO_T
@ -25,10 +24,10 @@
#define SI_MAX_SIZE 128
#define SI_PAD_SIZE ((SI_MAX_SIZE - __ARCH_SI_PREAMBLE_SIZE) / sizeof(int))
#define __ARCH_SI_UID_T __kernel_uid32_t
#define __ARCH_SI_UID_T __kernel_uid32_t
#ifndef __ARCH_SI_UID_T
#define __ARCH_SI_UID_T __kernel_uid32_t
#define __ARCH_SI_UID_T __kernel_uid32_t
#endif
#ifndef __ARCH_SI_BAND_T
@ -53,31 +52,31 @@ typedef struct siginfo {
/* kill() */
struct {
__kernel_pid_t _pid; /* sender's pid */
__ARCH_SI_UID_T _uid; /* sender's uid */
__kernel_pid_t _pid; /* sender's pid */
__ARCH_SI_UID_T _uid; /* sender's uid */
} _kill;
/* POSIX.1b timers */
struct {
__kernel_timer_t _tid; /* timer id */
int _overrun; /* overrun count */
char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)];
sigval_t _sigval; /* same as below */
int _sys_private; /* not to be passed to user */
__kernel_timer_t _tid; /* timer id */
int _overrun; /* overrun count */
char _pad[sizeof(__ARCH_SI_UID_T) - sizeof(int)];
sigval_t _sigval; /* same as below */
int _sys_private; /* not to be passed to user */
} _timer;
/* POSIX.1b signals */
struct {
__kernel_pid_t _pid; /* sender's pid */
__ARCH_SI_UID_T _uid; /* sender's uid */
__kernel_pid_t _pid; /* sender's pid */
__ARCH_SI_UID_T _uid; /* sender's uid */
sigval_t _sigval;
} _rt;
/* SIGCHLD */
struct {
__kernel_pid_t _pid; /* which child */
__ARCH_SI_UID_T _uid; /* sender's uid */
int _status; /* exit code */
__kernel_pid_t _pid; /* which child */
__ARCH_SI_UID_T _uid; /* sender's uid */
int _status; /* exit code */
__ARCH_SI_CLOCK_T _utime;
__ARCH_SI_CLOCK_T _stime;
} _sigchld;
@ -86,7 +85,7 @@ typedef struct siginfo {
struct {
void *_addr; /* faulting insn/memory ref. */
#ifdef __ARCH_SI_TRAPNO
int _trapno; /* TRAP # which caused the signal */
int _trapno; /* TRAP # which caused the signal */
#endif
short _addr_lsb; /* LSB of the reported address */
#ifndef __GENKSYMS__
@ -99,15 +98,15 @@ typedef struct siginfo {
/* SIGPOLL */
struct {
__ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
__ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
int _fd;
} _sigpoll;
/* SIGSYS */
struct {
void *_call_addr; /* calling user insn */
int _syscall; /* triggering system call number */
unsigned int _arch; /* AUDIT_ARCH_* of syscall */
int _syscall; /* triggering system call number */
unsigned int _arch; /* AUDIT_ARCH_* of syscall */
} _sigsys;
} _sifields;
} __ARCH_SI_ATTRIBUTES siginfo_t;
@ -119,6 +118,6 @@ typedef struct siginfo {
#undef SI_ASYNCIO
#undef SI_TIMER
#undef SI_MESGQ
#define SI_ASYNCIO -2 /* sent by AIO completion */
#define SI_ASYNCIO -2 /* sent by AIO completion */
#endif /* _UAPI_ASM_SIGINFO_H */

View File

@ -1,7 +1,7 @@
#ifndef COMPEL_ARCH_SYSCALL_TYPES_H__
#define COMPEL_ARCH_SYSCALL_TYPES_H__
#define SA_RESTORER 0x04000000U
#define SA_RESTORER 0x04000000U
typedef void rt_signalfn_t(int, siginfo_t *, void *);
typedef rt_signalfn_t *rt_sighandler_t;
@ -9,20 +9,20 @@ typedef rt_signalfn_t *rt_sighandler_t;
typedef void rt_restorefn_t(void);
typedef rt_restorefn_t *rt_sigrestore_t;
#define _KNSIG 64
#define _NSIG_BPW 64
#define _KNSIG 64
#define _NSIG_BPW 64
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
typedef struct {
unsigned long sig[_KNSIG_WORDS];
unsigned long sig[_KNSIG_WORDS];
} k_rtsigset_t;
typedef struct {
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
} rt_sigaction_t;
#endif /* COMPEL_ARCH_SYSCALL_TYPES_H__ */

View File

@ -5,8 +5,8 @@
#define ELF_PPC64
#define __handle_elf handle_elf_ppc64
#define arch_is_machine_supported(e_machine) (e_machine == EM_PPC64)
#define __handle_elf handle_elf_ppc64
#define arch_is_machine_supported(e_machine) (e_machine == EM_PPC64)
extern int handle_elf_ppc64(void *mem, size_t size);

View File

@ -1,4 +1,8 @@
#ifndef __COMPEL_SYSCALL_H__
#define __COMPEL_SYSCALL_H__
#define __NR(syscall, compat) ({ (void)compat; __NR_##syscall; })
#define __NR(syscall, compat) \
({ \
(void)compat; \
__NR_##syscall; \
})
#endif

View File

@ -4,7 +4,7 @@
#include <stdint.h>
typedef struct {
uint64_t hwcap[2];
uint64_t hwcap[2];
} compel_cpuinfo_t;
#endif /* UAPI_COMPEL_ASM_CPU_H__ */

View File

@ -5,8 +5,8 @@
#include <signal.h>
#include <stdint.h>
#define SIGMAX_OLD 31
#define SIGMAX 64
#define SIGMAX_OLD 31
#define SIGMAX 64
/*
* Copied from kernel header arch/powerpc/include/uapi/asm/ptrace.h
@ -15,44 +15,44 @@ typedef struct {
unsigned long gpr[32];
unsigned long nip;
unsigned long msr;
unsigned long orig_gpr3; /* Used for restarting system calls */
unsigned long orig_gpr3; /* Used for restarting system calls */
unsigned long ctr;
unsigned long link;
unsigned long xer;
unsigned long ccr;
unsigned long softe; /* Soft enabled/disabled */
unsigned long trap; /* Reason for being here */
unsigned long softe; /* Soft enabled/disabled */
unsigned long trap; /* Reason for being here */
/*
* N.B. for critical exceptions on 4xx, the dar and dsisr
* fields are overloaded to hold srr0 and srr1.
*/
unsigned long dar; /* Fault registers */
unsigned long dsisr; /* on 4xx/Book-E used for ESR */
unsigned long result; /* Result of a system call */
unsigned long dar; /* Fault registers */
unsigned long dsisr; /* on 4xx/Book-E used for ESR */
unsigned long result; /* Result of a system call */
} user_regs_struct_t;
#define NVSXREG 32
#define NVSXREG 32
#define USER_FPREGS_FL_FP 0x00001
#define USER_FPREGS_FL_ALTIVEC 0x00002
#define USER_FPREGS_FL_VSX 0x00004
#define USER_FPREGS_FL_TM 0x00010
#define USER_FPREGS_FL_FP 0x00001
#define USER_FPREGS_FL_ALTIVEC 0x00002
#define USER_FPREGS_FL_VSX 0x00004
#define USER_FPREGS_FL_TM 0x00010
#ifndef NT_PPC_TM_SPR
# define NT_PPC_TM_CGPR 0x108 /* TM checkpointed GPR Registers */
# define NT_PPC_TM_CFPR 0x109 /* TM checkpointed FPR Registers */
# define NT_PPC_TM_CVMX 0x10a /* TM checkpointed VMX Registers */
# define NT_PPC_TM_CVSX 0x10b /* TM checkpointed VSX Registers */
# define NT_PPC_TM_SPR 0x10c /* TM Special Purpose Registers */
#define NT_PPC_TM_CGPR 0x108 /* TM checkpointed GPR Registers */
#define NT_PPC_TM_CFPR 0x109 /* TM checkpointed FPR Registers */
#define NT_PPC_TM_CVMX 0x10a /* TM checkpointed VMX Registers */
#define NT_PPC_TM_CVSX 0x10b /* TM checkpointed VSX Registers */
#define NT_PPC_TM_SPR 0x10c /* TM Special Purpose Registers */
#endif
#define MSR_TMA (1UL<<34) /* bit 29 Trans Mem state: Transactional */
#define MSR_TMS (1UL<<33) /* bit 30 Trans Mem state: Suspended */
#define MSR_TM (1UL<<32) /* bit 31 Trans Mem Available */
#define MSR_VEC (1UL<<25)
#define MSR_VSX (1UL<<23)
#define MSR_TMA (1UL << 34) /* bit 29 Trans Mem state: Transactional */
#define MSR_TMS (1UL << 33) /* bit 30 Trans Mem state: Suspended */
#define MSR_TM (1UL << 32) /* bit 31 Trans Mem Available */
#define MSR_VEC (1UL << 25)
#define MSR_VSX (1UL << 23)
#define MSR_TM_ACTIVE(x) ((((x) & MSR_TM) && ((x)&(MSR_TMA|MSR_TMS))) != 0)
#define MSR_TM_ACTIVE(x) ((((x)&MSR_TM) && ((x) & (MSR_TMA | MSR_TMS))) != 0)
typedef struct {
uint64_t fpregs[NFPREG];
@ -72,19 +72,23 @@ typedef struct {
} tm;
} user_fpregs_struct_t;
#define REG_RES(regs) ((uint64_t)(regs).gpr[3])
#define REG_IP(regs) ((uint64_t)(regs).nip)
#define REG_SP(regs) ((uint64_t)(regs).gpr[1])
#define REG_SYSCALL_NR(regs) ((uint64_t)(regs).gpr[0])
#define REG_RES(regs) ((uint64_t)(regs).gpr[3])
#define REG_IP(regs) ((uint64_t)(regs).nip)
#define REG_SP(regs) ((uint64_t)(regs).gpr[1])
#define REG_SYSCALL_NR(regs) ((uint64_t)(regs).gpr[0])
#define user_regs_native(pregs) true
#define user_regs_native(pregs) true
#define ARCH_SI_TRAP TRAP_BRKPT
#define __NR(syscall, compat) ({ (void)compat; __NR_##syscall; })
#define __NR(syscall, compat) \
({ \
(void)compat; \
__NR_##syscall; \
})
#define __compel_arch_fetch_thread_area(tid, th) 0
#define compel_arch_fetch_thread_area(tctl) 0
#define compel_arch_fetch_thread_area(tctl) 0
#define compel_arch_get_tls_task(ctl, tls)
#define compel_arch_get_tls_thread(tctl, tls)

View File

@ -19,30 +19,31 @@
#include <compel/sigframe-common.h>
#define RT_SIGFRAME_OFFSET(rt_sigframe) 0
#define RT_SIGFRAME_OFFSET(rt_sigframe) 0
/* Copied from the Linux kernel header arch/powerpc/include/asm/ptrace.h */
#define USER_REDZONE_SIZE 512
#define USER_REDZONE_SIZE 512
/* Copied from the Linux kernel source file arch/powerpc/kernel/signal_64.c */
#define TRAMP_SIZE 6
#define TRAMP_SIZE 6
/*
* ucontext_t defined in /usr/include/powerpc64le-linux-gnu/sys/ucontext.h
*/
struct rt_sigframe {
/* sys_rt_sigreturn requires the ucontext be the first field */
ucontext_t uc;
ucontext_t uc_transact; /* Transactional state */
unsigned long _unused[2];
unsigned int tramp[TRAMP_SIZE];
struct rt_siginfo *pinfo;
void *puc;
struct rt_siginfo info;
/* New 64 bit little-endian ABI allows redzone of 512 bytes below sp */
char abigap[USER_REDZONE_SIZE];
/* sys_rt_sigreturn requires the ucontext be the first field */
ucontext_t uc;
ucontext_t uc_transact; /* Transactional state */
unsigned long _unused[2];
unsigned int tramp[TRAMP_SIZE];
struct rt_siginfo *pinfo;
void *puc;
struct rt_siginfo info;
/* New 64 bit little-endian ABI allows redzone of 512 bytes below sp */
char abigap[USER_REDZONE_SIZE];
} __attribute__((aligned(16)));
/* clang-format off */
#define ARCH_RT_SIGRETURN(new_sp, rt_sigframe) \
asm volatile( \
"mr 1, %0 \n" \
@ -51,29 +52,28 @@ struct rt_sigframe {
: \
: "r"(new_sp) \
: "memory")
/* clang-format on */
#if _CALL_ELF != 2
# error Only supporting ABIv2.
#error Only supporting ABIv2.
#else
# define FRAME_MIN_SIZE_PARM 96
#define FRAME_MIN_SIZE_PARM 96
#endif
#define RT_SIGFRAME_UC(rt_sigframe) (&(rt_sigframe)->uc)
#define RT_SIGFRAME_REGIP(rt_sigframe) ((long unsigned int)(rt_sigframe)->uc.uc_mcontext.gp_regs[PT_NIP])
#define RT_SIGFRAME_HAS_FPU(rt_sigframe) (1)
#define RT_SIGFRAME_FPU(rt_sigframe) (&(rt_sigframe)->uc.uc_mcontext)
#define RT_SIGFRAME_UC(rt_sigframe) (&(rt_sigframe)->uc)
#define RT_SIGFRAME_REGIP(rt_sigframe) ((long unsigned int)(rt_sigframe)->uc.uc_mcontext.gp_regs[PT_NIP])
#define RT_SIGFRAME_HAS_FPU(rt_sigframe) (1)
#define RT_SIGFRAME_FPU(rt_sigframe) (&(rt_sigframe)->uc.uc_mcontext)
#define rt_sigframe_erase_sigset(sigframe) \
memset(&sigframe->uc.uc_sigmask, 0, sizeof(k_rtsigset_t))
#define rt_sigframe_copy_sigset(sigframe, from) \
memcpy(&sigframe->uc.uc_sigmask, from, sizeof(k_rtsigset_t))
#define rt_sigframe_erase_sigset(sigframe) memset(&sigframe->uc.uc_sigmask, 0, sizeof(k_rtsigset_t))
#define rt_sigframe_copy_sigset(sigframe, from) memcpy(&sigframe->uc.uc_sigmask, from, sizeof(k_rtsigset_t))
#define MSR_TMA (1UL<<34) /* bit 29 Trans Mem state: Transactional */
#define MSR_TMS (1UL<<33) /* bit 30 Trans Mem state: Suspended */
#define MSR_TM (1UL<<32) /* bit 31 Trans Mem Available */
#define MSR_VEC (1UL<<25)
#define MSR_VSX (1UL<<23)
#define MSR_TMA (1UL << 34) /* bit 29 Trans Mem state: Transactional */
#define MSR_TMS (1UL << 33) /* bit 30 Trans Mem state: Suspended */
#define MSR_TM (1UL << 32) /* bit 31 Trans Mem Available */
#define MSR_VEC (1UL << 25)
#define MSR_VSX (1UL << 23)
#define MSR_TM_ACTIVE(x) ((((x) & MSR_TM) && ((x)&(MSR_TMA|MSR_TMS))) != 0)
#define MSR_TM_ACTIVE(x) ((((x)&MSR_TM) && ((x) & (MSR_TMA | MSR_TMS))) != 0)
#endif /* UAPI_COMPEL_ASM_SIGFRAME_H__ */

View File

@ -1,7 +1,7 @@
#ifndef COMPEL_ARCH_SYSCALL_TYPES_H__
#define COMPEL_ARCH_SYSCALL_TYPES_H__
#define SA_RESTORER 0x04000000U
#define SA_RESTORER 0x04000000U
typedef void rt_signalfn_t(int, siginfo_t *, void *);
typedef rt_signalfn_t *rt_sighandler_t;
@ -9,13 +9,13 @@ typedef rt_signalfn_t *rt_sighandler_t;
typedef void rt_restorefn_t(void);
typedef rt_restorefn_t *rt_sigrestore_t;
#define _KNSIG 64
#define _NSIG_BPW 64
#define _KNSIG 64
#define _NSIG_BPW 64
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
typedef struct {
unsigned long sig[_KNSIG_WORDS];
unsigned long sig[_KNSIG_WORDS];
} k_rtsigset_t;
/*
@ -23,10 +23,10 @@ typedef struct {
* include/linux/signal.h.
*/
typedef struct {
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
} rt_sigaction_t;
struct mmap_arg_struct;

View File

@ -5,8 +5,8 @@
#define ELF_S390
#define __handle_elf handle_elf_s390
#define arch_is_machine_supported(e_machine) (e_machine == EM_S390)
#define __handle_elf handle_elf_s390
#define arch_is_machine_supported(e_machine) (e_machine == EM_S390)
int handle_elf_s390(void *mem, size_t size);

View File

@ -1,8 +1,7 @@
#ifndef __COMPEL_SYSCALL_H__
#define __COMPEL_SYSCALL_H__
unsigned long sys_mmap(void *addr, unsigned long len, unsigned long prot,
unsigned long flags, unsigned long fd,
unsigned long sys_mmap(void *addr, unsigned long len, unsigned long prot, unsigned long flags, unsigned long fd,
unsigned long offset);
#endif

View File

@ -4,7 +4,7 @@
#include <stdint.h>
typedef struct {
uint64_t hwcap[2];
uint64_t hwcap[2];
} compel_cpuinfo_t;
#endif /* __CR_ASM_CPU_H__ */

View File

@ -7,8 +7,8 @@
#include <asm/ptrace.h>
#include "common/page.h"
#define SIGMAX 64
#define SIGMAX_OLD 31
#define SIGMAX 64
#define SIGMAX_OLD 31
/*
* Definitions from /usr/include/asm/ptrace.h:
@ -33,28 +33,28 @@ typedef struct {
} vector128_t;
struct prfpreg {
uint32_t fpc;
uint64_t fprs[16];
uint32_t fpc;
uint64_t fprs[16];
};
#define USER_FPREGS_VXRS 0x000000001
#define USER_FPREGS_VXRS 0x000000001
/* Guarded-storage control block */
#define USER_GS_CB 0x000000002
#define USER_GS_CB 0x000000002
/* Guarded-storage broadcast control block */
#define USER_GS_BC 0x000000004
#define USER_GS_BC 0x000000004
/* Runtime-instrumentation control block */
#define USER_RI_CB 0x000000008
#define USER_RI_CB 0x000000008
/* Runtime-instrumentation bit set */
#define USER_RI_ON 0x000000010
#define USER_RI_ON 0x000000010
typedef struct {
uint32_t flags;
struct prfpreg prfpreg;
uint64_t vxrs_low[16];
vector128_t vxrs_high[16];
uint64_t gs_cb[4];
uint64_t gs_bc[4];
uint64_t ri_cb[8];
uint32_t flags;
struct prfpreg prfpreg;
uint64_t vxrs_low[16];
vector128_t vxrs_high[16];
uint64_t gs_cb[4];
uint64_t gs_bc[4];
uint64_t ri_cb[8];
} user_fpregs_struct_t;
typedef struct {
@ -62,18 +62,22 @@ typedef struct {
uint32_t system_call;
} user_regs_struct_t;
#define REG_RES(r) ((uint64_t)(r).prstatus.gprs[2])
#define REG_IP(r) ((uint64_t)(r).prstatus.psw.addr)
#define REG_SP(r) ((uint64_t)(r).prstatus.gprs[15])
#define REG_RES(r) ((uint64_t)(r).prstatus.gprs[2])
#define REG_IP(r) ((uint64_t)(r).prstatus.psw.addr)
#define REG_SP(r) ((uint64_t)(r).prstatus.gprs[15])
/*
* We assume that REG_SYSCALL_NR() is only used for pie code where we
* always use svc 0 with opcode in %r1.
*/
#define REG_SYSCALL_NR(r) ((uint64_t)(r).prstatus.gprs[1])
#define REG_SYSCALL_NR(r) ((uint64_t)(r).prstatus.gprs[1])
#define user_regs_native(pregs) true
#define user_regs_native(pregs) true
#define __NR(syscall, compat) ({ (void)compat; __NR_##syscall; })
#define __NR(syscall, compat) \
({ \
(void)compat; \
__NR_##syscall; \
})
struct mmap_arg_struct {
unsigned long addr;
@ -85,7 +89,7 @@ struct mmap_arg_struct {
};
#define __compel_arch_fetch_thread_area(tid, th) 0
#define compel_arch_fetch_thread_area(tctl) 0
#define compel_arch_fetch_thread_area(tctl) 0
#define compel_arch_get_tls_task(ctl, tls)
#define compel_arch_get_tls_thread(tctl, tls)

View File

@ -36,14 +36,14 @@ typedef struct {
* From /usr/include/uapi/asm/ucontext.h
*/
struct ucontext_extended {
unsigned long uc_flags;
ucontext_t *uc_link;
stack_t uc_stack;
_sigregs uc_mcontext;
sigset_t uc_sigmask;
unsigned long uc_flags;
ucontext_t *uc_link;
stack_t uc_stack;
_sigregs uc_mcontext;
sigset_t uc_sigmask;
/* Allow for uc_sigmask growth. Glibc uses a 1024-bit sigset_t. */
unsigned char __unused[128 - sizeof(sigset_t)];
_sigregs_ext uc_mcontext_ext;
unsigned char __unused[128 - sizeof(sigset_t)];
_sigregs_ext uc_mcontext_ext;
};
/*
@ -59,6 +59,7 @@ struct rt_sigframe {
/*
* Do rt_sigreturn SVC
*/
/* clang-format off */
#define ARCH_RT_SIGRETURN(new_sp, rt_sigframe) \
asm volatile( \
"lgr %%r15,%0\n" \
@ -67,14 +68,13 @@ struct rt_sigframe {
: \
: "d" (new_sp) \
: "memory")
/* clang-format on */
#define RT_SIGFRAME_UC(rt_sigframe) (&rt_sigframe->uc)
#define RT_SIGFRAME_REGIP(rt_sigframe) (rt_sigframe)->uc.uc_mcontext.regs.psw.addr
#define RT_SIGFRAME_HAS_FPU(rt_sigframe) (1)
#define RT_SIGFRAME_UC(rt_sigframe) (&rt_sigframe->uc)
#define RT_SIGFRAME_REGIP(rt_sigframe) (rt_sigframe)->uc.uc_mcontext.regs.psw.addr
#define RT_SIGFRAME_HAS_FPU(rt_sigframe) (1)
#define rt_sigframe_erase_sigset(sigframe) \
memset(&sigframe->uc.uc_sigmask, 0, sizeof(k_rtsigset_t))
#define rt_sigframe_copy_sigset(sigframe, from) \
memcpy(&sigframe->uc.uc_sigmask, from, sizeof(k_rtsigset_t))
#define rt_sigframe_erase_sigset(sigframe) memset(&sigframe->uc.uc_sigmask, 0, sizeof(k_rtsigset_t))
#define rt_sigframe_copy_sigset(sigframe, from) memcpy(&sigframe->uc.uc_sigmask, from, sizeof(k_rtsigset_t))
#endif /* UAPI_COMPEL_ASM_SIGFRAME_H__ */

View File

@ -9,17 +9,16 @@
#include <errno.h>
#define sys_recv(sockfd, ubuf, size, flags) \
sys_recvfrom(sockfd, ubuf, size, flags, NULL, NULL)
#define sys_recv(sockfd, ubuf, size, flags) sys_recvfrom(sockfd, ubuf, size, flags, NULL, NULL)
typedef struct prologue_init_args {
struct sockaddr_un ctl_sock_addr;
unsigned int ctl_sock_addr_len;
struct sockaddr_un ctl_sock_addr;
unsigned int ctl_sock_addr_len;
unsigned int arg_s;
void *arg_p;
unsigned int arg_s;
void *arg_p;
void *sigframe;
void *sigframe;
} prologue_init_args_t;
#endif /* __ASSEMBLY__ */
@ -29,8 +28,8 @@ typedef struct prologue_init_args {
*
* FIXME It is rather should be taken from sigframe header.
*/
#define PROLOGUE_SGFRAME_SIZE 4096
#define PROLOGUE_SGFRAME_SIZE 4096
#define PROLOGUE_INIT_ARGS_SIZE 1024
#define PROLOGUE_INIT_ARGS_SIZE 1024
#endif /* __ASM_PROLOGUE_H__ */

View File

@ -8,12 +8,12 @@ typedef rt_signalfn_t *rt_sighandler_t;
typedef void rt_restorefn_t(void);
typedef rt_restorefn_t *rt_sigrestore_t;
#define SA_RESTORER 0x04000000
#define SA_RESTORER 0x04000000
#define _KNSIG 64
#define _NSIG_BPW 64
#define _KNSIG 64
#define _NSIG_BPW 64
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
#define _KNSIG_WORDS (_KNSIG / _NSIG_BPW)
/*
* Note: as k_rtsigset_t is the same size for 32-bit and 64-bit,
@ -21,14 +21,14 @@ typedef rt_restorefn_t *rt_sigrestore_t;
* purpose if we ever going to support native 32-bit compilation.
*/
typedef struct {
uint64_t sig[_KNSIG_WORDS];
uint64_t sig[_KNSIG_WORDS];
} k_rtsigset_t;
typedef struct {
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
rt_sighandler_t rt_sa_handler;
unsigned long rt_sa_flags;
rt_sigrestore_t rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
} rt_sigaction_t;
/*
@ -37,24 +37,24 @@ typedef struct {
* with unaligned rt_sa_mask.
*/
typedef struct __attribute__((packed)) {
unsigned int rt_sa_handler;
unsigned int rt_sa_flags;
unsigned int rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
unsigned int rt_sa_handler;
unsigned int rt_sa_flags;
unsigned int rt_sa_restorer;
k_rtsigset_t rt_sa_mask;
} rt_sigaction_t_compat;
/* Types for set_thread_area, get_thread_area syscalls */
typedef struct {
unsigned int entry_number;
unsigned int base_addr;
unsigned int limit;
unsigned int seg_32bit:1;
unsigned int contents:2;
unsigned int read_exec_only:1;
unsigned int limit_in_pages:1;
unsigned int seg_not_present:1;
unsigned int useable:1;
unsigned int lm:1;
unsigned int entry_number;
unsigned int base_addr;
unsigned int limit;
unsigned int seg_32bit : 1;
unsigned int contents : 2;
unsigned int read_exec_only : 1;
unsigned int limit_in_pages : 1;
unsigned int seg_not_present : 1;
unsigned int useable : 1;
unsigned int lm : 1;
} user_desc_t;
#endif /* COMPEL_ARCH_SYSCALL_TYPES_H__ */

View File

@ -1,31 +1,21 @@
#ifndef __COMPEL_ASM_CPU_H__
#define __COMPEL_ASM_CPU_H__
static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx)
static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
{
/* ecx is often an input as well as an output. */
asm volatile("cpuid"
: "=a" (*eax),
"=b" (*ebx),
"=c" (*ecx),
"=d" (*edx)
: "0" (*eax), "2" (*ecx)
: "memory");
asm volatile("cpuid" : "=a"(*eax), "=b"(*ebx), "=c"(*ecx), "=d"(*edx) : "0"(*eax), "2"(*ecx) : "memory");
}
static inline void cpuid(unsigned int op,
unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx)
static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
{
*eax = op;
*ecx = 0;
native_cpuid(eax, ebx, ecx, edx);
}
static inline void cpuid_count(unsigned int op, int count,
unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx)
static inline void cpuid_count(unsigned int op, int count, unsigned int *eax, unsigned int *ebx, unsigned int *ecx,
unsigned int *edx)
{
*eax = op;
*ecx = count;

View File

@ -6,15 +6,15 @@
#define ELF_X86_64
#ifndef R_X86_64_GOTPCRELX
# define R_X86_64_GOTPCRELX 41
#define R_X86_64_GOTPCRELX 41
#endif
#ifndef R_X86_64_REX_GOTPCRELX
# define R_X86_64_REX_GOTPCRELX 42
#define R_X86_64_REX_GOTPCRELX 42
#endif
#define __handle_elf handle_elf_x86_64
#define arch_is_machine_supported(e_machine) (e_machine == EM_X86_64)
#define __handle_elf handle_elf_x86_64
#define arch_is_machine_supported(e_machine) (e_machine == EM_X86_64)
extern int handle_elf_x86_32(void *mem, size_t size);
extern int handle_elf_x86_64(void *mem, size_t size);

View File

@ -1,6 +1,6 @@
#ifndef __COMPEL_SYSCALL_H__
#define __COMPEL_SYSCALL_H__
#define __NR(syscall, compat) ((compat) ? __NR32_##syscall : __NR_##syscall)
#define __NR(syscall, compat) ((compat) ? __NR32_##syscall : __NR_##syscall)
/*
* For x86_32 __NR_mmap inside the kernel represents old_mmap system

View File

@ -15,334 +15,334 @@
* to keep it here, since it's an ABI now.
*/
enum cpuid_leafs {
CPUID_1_EDX = 0,
CPUID_8000_0001_EDX = 1,
CPUID_8086_0001_EDX = 2,
CPUID_LNX_1 = 3,
CPUID_1_ECX = 4,
CPUID_C000_0001_EDX = 5,
CPUID_8000_0001_ECX = 6,
CPUID_LNX_2 = 7,
CPUID_LNX_3 = 8,
CPUID_7_0_EBX = 9,
CPUID_D_1_EAX = 10,
CPUID_7_0_ECX = 11,
CPUID_F_1_EDX = 12,
CPUID_8000_0008_EBX = 13,
CPUID_6_EAX = 14,
CPUID_8000_000A_EDX = 15,
CPUID_F_0_EDX = 16,
CPUID_8000_0007_EBX = 17,
CPUID_7_0_EDX = 18,
CPUID_1_EDX = 0,
CPUID_8000_0001_EDX = 1,
CPUID_8086_0001_EDX = 2,
CPUID_LNX_1 = 3,
CPUID_1_ECX = 4,
CPUID_C000_0001_EDX = 5,
CPUID_8000_0001_ECX = 6,
CPUID_LNX_2 = 7,
CPUID_LNX_3 = 8,
CPUID_7_0_EBX = 9,
CPUID_D_1_EAX = 10,
CPUID_7_0_ECX = 11,
CPUID_F_1_EDX = 12,
CPUID_8000_0008_EBX = 13,
CPUID_6_EAX = 14,
CPUID_8000_000A_EDX = 15,
CPUID_F_0_EDX = 16,
CPUID_8000_0007_EBX = 17,
CPUID_7_0_EDX = 18,
};
#define NCAPINTS_V1 12
#define NCAPINTS_V2 19
#define NCAPINTS_V1 12
#define NCAPINTS_V2 19
#define NCAPINTS (NCAPINTS_V2) /* N 32-bit words worth of info */
#define NCAPINTS_BITS (NCAPINTS * 32)
#define NCAPINTS (NCAPINTS_V2) /* N 32-bit words worth of info */
#define NCAPINTS_BITS (NCAPINTS * 32)
/* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */
#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */
#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */
#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
#define X86_FEATURE_CLFLUSH (0*32+19) /* CLFLUSH instruction */
#define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */
#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
#define X86_FEATURE_XMM (0*32+25) /* "sse" */
#define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */
#define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */
#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
#define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */
#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
#define X86_FEATURE_FPU (0 * 32 + 0) /* Onboard FPU */
#define X86_FEATURE_VME (0 * 32 + 1) /* Virtual Mode Extensions */
#define X86_FEATURE_DE (0 * 32 + 2) /* Debugging Extensions */
#define X86_FEATURE_PSE (0 * 32 + 3) /* Page Size Extensions */
#define X86_FEATURE_TSC (0 * 32 + 4) /* Time Stamp Counter */
#define X86_FEATURE_MSR (0 * 32 + 5) /* Model-Specific Registers */
#define X86_FEATURE_PAE (0 * 32 + 6) /* Physical Address Extensions */
#define X86_FEATURE_MCE (0 * 32 + 7) /* Machine Check Exception */
#define X86_FEATURE_CX8 (0 * 32 + 8) /* CMPXCHG8 instruction */
#define X86_FEATURE_APIC (0 * 32 + 9) /* Onboard APIC */
#define X86_FEATURE_SEP (0 * 32 + 11) /* SYSENTER/SYSEXIT */
#define X86_FEATURE_MTRR (0 * 32 + 12) /* Memory Type Range Registers */
#define X86_FEATURE_PGE (0 * 32 + 13) /* Page Global Enable */
#define X86_FEATURE_MCA (0 * 32 + 14) /* Machine Check Architecture */
#define X86_FEATURE_CMOV (0 * 32 + 15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */
#define X86_FEATURE_PAT (0 * 32 + 16) /* Page Attribute Table */
#define X86_FEATURE_PSE36 (0 * 32 + 17) /* 36-bit PSEs */
#define X86_FEATURE_PN (0 * 32 + 18) /* Processor serial number */
#define X86_FEATURE_CLFLUSH (0 * 32 + 19) /* CLFLUSH instruction */
#define X86_FEATURE_DS (0 * 32 + 21) /* "dts" Debug Store */
#define X86_FEATURE_ACPI (0 * 32 + 22) /* ACPI via MSR */
#define X86_FEATURE_MMX (0 * 32 + 23) /* Multimedia Extensions */
#define X86_FEATURE_FXSR (0 * 32 + 24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
#define X86_FEATURE_XMM (0 * 32 + 25) /* "sse" */
#define X86_FEATURE_XMM2 (0 * 32 + 26) /* "sse2" */
#define X86_FEATURE_SELFSNOOP (0 * 32 + 27) /* "ss" CPU self snoop */
#define X86_FEATURE_HT (0 * 32 + 28) /* Hyper-Threading */
#define X86_FEATURE_ACC (0 * 32 + 29) /* "tm" Automatic clock control */
#define X86_FEATURE_IA64 (0 * 32 + 30) /* IA-64 processor */
#define X86_FEATURE_PBE (0 * 32 + 31) /* Pending Break Enable */
/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
/* Don't duplicate feature flags which are redundant with Intel! */
#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
#define X86_FEATURE_MP (1*32+19) /* MP Capable */
#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
#define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */
#define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */
#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64, 64-bit support) */
#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow extensions */
#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow */
#define X86_FEATURE_SYSCALL (1 * 32 + 11) /* SYSCALL/SYSRET */
#define X86_FEATURE_MP (1 * 32 + 19) /* MP Capable */
#define X86_FEATURE_NX (1 * 32 + 20) /* Execute Disable */
#define X86_FEATURE_MMXEXT (1 * 32 + 22) /* AMD MMX extensions */
#define X86_FEATURE_FXSR_OPT (1 * 32 + 25) /* FXSAVE/FXRSTOR optimizations */
#define X86_FEATURE_GBPAGES (1 * 32 + 26) /* "pdpe1gb" GB pages */
#define X86_FEATURE_RDTSCP (1 * 32 + 27) /* RDTSCP */
#define X86_FEATURE_LM (1 * 32 + 29) /* Long Mode (x86-64, 64-bit support) */
#define X86_FEATURE_3DNOWEXT (1 * 32 + 30) /* AMD 3DNow extensions */
#define X86_FEATURE_3DNOW (1 * 32 + 31) /* 3DNow */
/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
#define X86_FEATURE_RECOVERY (2 * 32 + 0) /* CPU in recovery mode */
#define X86_FEATURE_LONGRUN (2 * 32 + 1) /* Longrun power control */
#define X86_FEATURE_LRTI (2 * 32 + 3) /* LongRun table interface */
/* Other features, Linux-defined mapping, word 3 */
/* This range is used for feature bits which conflict or are synthesized */
#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
#define X86_FEATURE_CXMMX (3 * 32 + 0) /* Cyrix MMX extensions */
#define X86_FEATURE_K6_MTRR (3 * 32 + 1) /* AMD K6 nonstandard MTRRs */
#define X86_FEATURE_CYRIX_ARR (3 * 32 + 2) /* Cyrix ARRs (= MTRRs) */
#define X86_FEATURE_CENTAUR_MCR (3 * 32 + 3) /* Centaur MCRs (= MTRRs) */
/* CPU types for specific tunings: */
#define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */
#define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */
#define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */
#define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */
#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
#define X86_FEATURE_UP (3*32+ 9) /* SMP kernel running on UP */
#define X86_FEATURE_ART (3*32+10) /* Always running timer (ART) */
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
#define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in IA32 userspace */
#define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in IA32 userspace */
#define X86_FEATURE_REP_GOOD (3*32+16) /* REP microcode works well */
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" MFENCE synchronizes RDTSC */
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" LFENCE synchronizes RDTSC */
#define X86_FEATURE_ACC_POWER (3*32+19) /* AMD Accumulated Power Mechanism */
#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
#define X86_FEATURE_ALWAYS (3*32+21) /* "" Always-present feature */
#define X86_FEATURE_XTOPOLOGY (3*32+22) /* CPU topology enum extensions */
#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
#define X86_FEATURE_CPUID (3*32+25) /* CPU has CPUID instruction itself */
#define X86_FEATURE_EXTD_APICID (3*32+26) /* Extended APICID (8 bits) */
#define X86_FEATURE_AMD_DCM (3*32+27) /* AMD multi-node processor */
#define X86_FEATURE_APERFMPERF (3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
#define X86_FEATURE_NONSTOP_TSC_S3 (3*32+30) /* TSC doesn't stop in S3 state */
#define X86_FEATURE_TSC_KNOWN_FREQ (3*32+31) /* TSC has known frequency */
#define X86_FEATURE_K8 (3 * 32 + 4) /* "" Opteron, Athlon64 */
#define X86_FEATURE_K7 (3 * 32 + 5) /* "" Athlon */
#define X86_FEATURE_P3 (3 * 32 + 6) /* "" P3 */
#define X86_FEATURE_P4 (3 * 32 + 7) /* "" P4 */
#define X86_FEATURE_CONSTANT_TSC (3 * 32 + 8) /* TSC ticks at a constant rate */
#define X86_FEATURE_UP (3 * 32 + 9) /* SMP kernel running on UP */
#define X86_FEATURE_ART (3 * 32 + 10) /* Always running timer (ART) */
#define X86_FEATURE_ARCH_PERFMON (3 * 32 + 11) /* Intel Architectural PerfMon */
#define X86_FEATURE_PEBS (3 * 32 + 12) /* Precise-Event Based Sampling */
#define X86_FEATURE_BTS (3 * 32 + 13) /* Branch Trace Store */
#define X86_FEATURE_SYSCALL32 (3 * 32 + 14) /* "" syscall in IA32 userspace */
#define X86_FEATURE_SYSENTER32 (3 * 32 + 15) /* "" sysenter in IA32 userspace */
#define X86_FEATURE_REP_GOOD (3 * 32 + 16) /* REP microcode works well */
#define X86_FEATURE_MFENCE_RDTSC (3 * 32 + 17) /* "" MFENCE synchronizes RDTSC */
#define X86_FEATURE_LFENCE_RDTSC (3 * 32 + 18) /* "" LFENCE synchronizes RDTSC */
#define X86_FEATURE_ACC_POWER (3 * 32 + 19) /* AMD Accumulated Power Mechanism */
#define X86_FEATURE_NOPL (3 * 32 + 20) /* The NOPL (0F 1F) instructions */
#define X86_FEATURE_ALWAYS (3 * 32 + 21) /* "" Always-present feature */
#define X86_FEATURE_XTOPOLOGY (3 * 32 + 22) /* CPU topology enum extensions */
#define X86_FEATURE_TSC_RELIABLE (3 * 32 + 23) /* TSC is known to be reliable */
#define X86_FEATURE_NONSTOP_TSC (3 * 32 + 24) /* TSC does not stop in C states */
#define X86_FEATURE_CPUID (3 * 32 + 25) /* CPU has CPUID instruction itself */
#define X86_FEATURE_EXTD_APICID (3 * 32 + 26) /* Extended APICID (8 bits) */
#define X86_FEATURE_AMD_DCM (3 * 32 + 27) /* AMD multi-node processor */
#define X86_FEATURE_APERFMPERF (3 * 32 + 28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
#define X86_FEATURE_NONSTOP_TSC_S3 (3 * 32 + 30) /* TSC doesn't stop in S3 state */
#define X86_FEATURE_TSC_KNOWN_FREQ (3 * 32 + 31) /* TSC has known frequency */
/* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" MONITOR/MWAIT support */
#define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
#define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */
#define X86_FEATURE_SMX (4*32+ 6) /* Safer Mode eXtensions */
#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
#define X86_FEATURE_CID (4*32+10) /* Context ID */
#define X86_FEATURE_SDBG (4*32+11) /* Silicon Debug */
#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B instruction */
#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
#define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capabilities MSR */
#define X86_FEATURE_PCID (4*32+17) /* Process Context Identifiers */
#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
#define X86_FEATURE_X2APIC (4*32+21) /* X2APIC */
#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */
#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
#define X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* TSC deadline timer */
#define X86_FEATURE_AES (4*32+25) /* AES instructions */
#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */
#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE instruction enabled in the OS */
#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
#define X86_FEATURE_F16C (4*32+29) /* 16-bit FP conversions */
#define X86_FEATURE_RDRAND (4*32+30) /* RDRAND instruction */
#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */
#define X86_FEATURE_XMM3 (4 * 32 + 0) /* "pni" SSE-3 */
#define X86_FEATURE_PCLMULQDQ (4 * 32 + 1) /* PCLMULQDQ instruction */
#define X86_FEATURE_DTES64 (4 * 32 + 2) /* 64-bit Debug Store */
#define X86_FEATURE_MWAIT (4 * 32 + 3) /* "monitor" MONITOR/MWAIT support */
#define X86_FEATURE_DSCPL (4 * 32 + 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
#define X86_FEATURE_VMX (4 * 32 + 5) /* Hardware virtualization */
#define X86_FEATURE_SMX (4 * 32 + 6) /* Safer Mode eXtensions */
#define X86_FEATURE_EST (4 * 32 + 7) /* Enhanced SpeedStep */
#define X86_FEATURE_TM2 (4 * 32 + 8) /* Thermal Monitor 2 */
#define X86_FEATURE_SSSE3 (4 * 32 + 9) /* Supplemental SSE-3 */
#define X86_FEATURE_CID (4 * 32 + 10) /* Context ID */
#define X86_FEATURE_SDBG (4 * 32 + 11) /* Silicon Debug */
#define X86_FEATURE_FMA (4 * 32 + 12) /* Fused multiply-add */
#define X86_FEATURE_CX16 (4 * 32 + 13) /* CMPXCHG16B instruction */
#define X86_FEATURE_XTPR (4 * 32 + 14) /* Send Task Priority Messages */
#define X86_FEATURE_PDCM (4 * 32 + 15) /* Perf/Debug Capabilities MSR */
#define X86_FEATURE_PCID (4 * 32 + 17) /* Process Context Identifiers */
#define X86_FEATURE_DCA (4 * 32 + 18) /* Direct Cache Access */
#define X86_FEATURE_XMM4_1 (4 * 32 + 19) /* "sse4_1" SSE-4.1 */
#define X86_FEATURE_XMM4_2 (4 * 32 + 20) /* "sse4_2" SSE-4.2 */
#define X86_FEATURE_X2APIC (4 * 32 + 21) /* X2APIC */
#define X86_FEATURE_MOVBE (4 * 32 + 22) /* MOVBE instruction */
#define X86_FEATURE_POPCNT (4 * 32 + 23) /* POPCNT instruction */
#define X86_FEATURE_TSC_DEADLINE_TIMER (4 * 32 + 24) /* TSC deadline timer */
#define X86_FEATURE_AES (4 * 32 + 25) /* AES instructions */
#define X86_FEATURE_XSAVE (4 * 32 + 26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */
#define X86_FEATURE_OSXSAVE (4 * 32 + 27) /* "" XSAVE instruction enabled in the OS */
#define X86_FEATURE_AVX (4 * 32 + 28) /* Advanced Vector Extensions */
#define X86_FEATURE_F16C (4 * 32 + 29) /* 16-bit FP conversions */
#define X86_FEATURE_RDRAND (4 * 32 + 30) /* RDRAND instruction */
#define X86_FEATURE_HYPERVISOR (4 * 32 + 31) /* Running on a hypervisor */
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
#define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */
#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */
#define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */
#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
#define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */
#define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */
#define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */
#define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */
#define X86_FEATURE_XSTORE (5 * 32 + 2) /* "rng" RNG present (xstore) */
#define X86_FEATURE_XSTORE_EN (5 * 32 + 3) /* "rng_en" RNG enabled */
#define X86_FEATURE_XCRYPT (5 * 32 + 6) /* "ace" on-CPU crypto (xcrypt) */
#define X86_FEATURE_XCRYPT_EN (5 * 32 + 7) /* "ace_en" on-CPU crypto enabled */
#define X86_FEATURE_ACE2 (5 * 32 + 8) /* Advanced Cryptography Engine v2 */
#define X86_FEATURE_ACE2_EN (5 * 32 + 9) /* ACE v2 enabled */
#define X86_FEATURE_PHE (5 * 32 + 10) /* PadLock Hash Engine */
#define X86_FEATURE_PHE_EN (5 * 32 + 11) /* PHE enabled */
#define X86_FEATURE_PMM (5 * 32 + 12) /* PadLock Montgomery Multiplier */
#define X86_FEATURE_PMM_EN (5 * 32 + 13) /* PMM enabled */
/* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */
#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
#define X86_FEATURE_SVM (6*32+ 2) /* Secure Virtual Machine */
#define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */
#define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */
#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */
#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */
#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */
#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */
#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */
#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
#define X86_FEATURE_TCE (6*32+17) /* Translation Cache Extension */
#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */
#define X86_FEATURE_TBM (6*32+21) /* Trailing Bit Manipulations */
#define X86_FEATURE_TOPOEXT (6*32+22) /* Topology extensions CPUID leafs */
#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* Core performance counter extensions */
#define X86_FEATURE_PERFCTR_NB (6*32+24) /* NB performance counter extensions */
#define X86_FEATURE_BPEXT (6*32+26) /* Data breakpoint extension */
#define X86_FEATURE_PTSC (6*32+27) /* Performance time-stamp counter */
#define X86_FEATURE_PERFCTR_LLC (6*32+28) /* Last Level Cache performance counter extensions */
#define X86_FEATURE_MWAITX (6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */
#define X86_FEATURE_LAHF_LM (6 * 32 + 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY (6 * 32 + 1) /* If yes HyperThreading not valid */
#define X86_FEATURE_SVM (6 * 32 + 2) /* Secure Virtual Machine */
#define X86_FEATURE_EXTAPIC (6 * 32 + 3) /* Extended APIC space */
#define X86_FEATURE_CR8_LEGACY (6 * 32 + 4) /* CR8 in 32-bit mode */
#define X86_FEATURE_ABM (6 * 32 + 5) /* Advanced bit manipulation */
#define X86_FEATURE_SSE4A (6 * 32 + 6) /* SSE-4A */
#define X86_FEATURE_MISALIGNSSE (6 * 32 + 7) /* Misaligned SSE mode */
#define X86_FEATURE_3DNOWPREFETCH (6 * 32 + 8) /* 3DNow prefetch instructions */
#define X86_FEATURE_OSVW (6 * 32 + 9) /* OS Visible Workaround */
#define X86_FEATURE_IBS (6 * 32 + 10) /* Instruction Based Sampling */
#define X86_FEATURE_XOP (6 * 32 + 11) /* extended AVX instructions */
#define X86_FEATURE_SKINIT (6 * 32 + 12) /* SKINIT/STGI instructions */
#define X86_FEATURE_WDT (6 * 32 + 13) /* Watchdog timer */
#define X86_FEATURE_LWP (6 * 32 + 15) /* Light Weight Profiling */
#define X86_FEATURE_FMA4 (6 * 32 + 16) /* 4 operands MAC instructions */
#define X86_FEATURE_TCE (6 * 32 + 17) /* Translation Cache Extension */
#define X86_FEATURE_NODEID_MSR (6 * 32 + 19) /* NodeId MSR */
#define X86_FEATURE_TBM (6 * 32 + 21) /* Trailing Bit Manipulations */
#define X86_FEATURE_TOPOEXT (6 * 32 + 22) /* Topology extensions CPUID leafs */
#define X86_FEATURE_PERFCTR_CORE (6 * 32 + 23) /* Core performance counter extensions */
#define X86_FEATURE_PERFCTR_NB (6 * 32 + 24) /* NB performance counter extensions */
#define X86_FEATURE_BPEXT (6 * 32 + 26) /* Data breakpoint extension */
#define X86_FEATURE_PTSC (6 * 32 + 27) /* Performance time-stamp counter */
#define X86_FEATURE_PERFCTR_LLC (6 * 32 + 28) /* Last Level Cache performance counter extensions */
#define X86_FEATURE_MWAITX (6 * 32 + 29) /* MWAIT extension (MONITORX/MWAITX instructions) */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
#define X86_FEATURE_FSGSBASE (9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
#define X86_FEATURE_TSC_ADJUST (9*32+ 1) /* TSC adjustment MSR 0x3B */
#define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */
#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */
#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */
#define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */
#define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */
#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */
#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
#define X86_FEATURE_CQM (9*32+12) /* Cache QoS Monitoring */
#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
#define X86_FEATURE_RDT_A (9*32+15) /* Resource Director Technology Allocation */
#define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */
#define X86_FEATURE_AVX512DQ (9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
#define X86_FEATURE_RDSEED (9*32+18) /* RDSEED instruction */
#define X86_FEATURE_ADX (9*32+19) /* ADCX and ADOX instructions */
#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
#define X86_FEATURE_AVX512IFMA (9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
#define X86_FEATURE_CLFLUSHOPT (9*32+23) /* CLFLUSHOPT instruction */
#define X86_FEATURE_CLWB (9*32+24) /* CLWB instruction */
#define X86_FEATURE_INTEL_PT (9*32+25) /* Intel Processor Trace */
#define X86_FEATURE_AVX512PF (9*32+26) /* AVX-512 Prefetch */
#define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */
#define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */
#define X86_FEATURE_SHA_NI (9*32+29) /* SHA1/SHA256 Instruction Extensions */
#define X86_FEATURE_AVX512BW (9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
#define X86_FEATURE_AVX512VL (9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
#define X86_FEATURE_FSGSBASE (9 * 32 + 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
#define X86_FEATURE_TSC_ADJUST (9 * 32 + 1) /* TSC adjustment MSR 0x3B */
#define X86_FEATURE_BMI1 (9 * 32 + 3) /* 1st group bit manipulation extensions */
#define X86_FEATURE_HLE (9 * 32 + 4) /* Hardware Lock Elision */
#define X86_FEATURE_AVX2 (9 * 32 + 5) /* AVX2 instructions */
#define X86_FEATURE_SMEP (9 * 32 + 7) /* Supervisor Mode Execution Protection */
#define X86_FEATURE_BMI2 (9 * 32 + 8) /* 2nd group bit manipulation extensions */
#define X86_FEATURE_ERMS (9 * 32 + 9) /* Enhanced REP MOVSB/STOSB instructions */
#define X86_FEATURE_INVPCID (9 * 32 + 10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM (9 * 32 + 11) /* Restricted Transactional Memory */
#define X86_FEATURE_CQM (9 * 32 + 12) /* Cache QoS Monitoring */
#define X86_FEATURE_MPX (9 * 32 + 14) /* Memory Protection Extension */
#define X86_FEATURE_RDT_A (9 * 32 + 15) /* Resource Director Technology Allocation */
#define X86_FEATURE_AVX512F (9 * 32 + 16) /* AVX-512 Foundation */
#define X86_FEATURE_AVX512DQ (9 * 32 + 17) /* AVX-512 DQ (Double/Quad granular) Instructions */
#define X86_FEATURE_RDSEED (9 * 32 + 18) /* RDSEED instruction */
#define X86_FEATURE_ADX (9 * 32 + 19) /* ADCX and ADOX instructions */
#define X86_FEATURE_SMAP (9 * 32 + 20) /* Supervisor Mode Access Prevention */
#define X86_FEATURE_AVX512IFMA (9 * 32 + 21) /* AVX-512 Integer Fused Multiply-Add instructions */
#define X86_FEATURE_CLFLUSHOPT (9 * 32 + 23) /* CLFLUSHOPT instruction */
#define X86_FEATURE_CLWB (9 * 32 + 24) /* CLWB instruction */
#define X86_FEATURE_INTEL_PT (9 * 32 + 25) /* Intel Processor Trace */
#define X86_FEATURE_AVX512PF (9 * 32 + 26) /* AVX-512 Prefetch */
#define X86_FEATURE_AVX512ER (9 * 32 + 27) /* AVX-512 Exponential and Reciprocal */
#define X86_FEATURE_AVX512CD (9 * 32 + 28) /* AVX-512 Conflict Detection */
#define X86_FEATURE_SHA_NI (9 * 32 + 29) /* SHA1/SHA256 Instruction Extensions */
#define X86_FEATURE_AVX512BW (9 * 32 + 30) /* AVX-512 BW (Byte/Word granular) Instructions */
#define X86_FEATURE_AVX512VL (9 * 32 + 31) /* AVX-512 VL (128/256 Vector Length) Extensions */
/* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */
#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */
#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC instruction */
#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */
#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */
#define X86_FEATURE_XSAVEOPT (10 * 32 + 0) /* XSAVEOPT instruction */
#define X86_FEATURE_XSAVEC (10 * 32 + 1) /* XSAVEC instruction */
#define X86_FEATURE_XGETBV1 (10 * 32 + 2) /* XGETBV with ECX = 1 instruction */
#define X86_FEATURE_XSAVES (10 * 32 + 3) /* XSAVES/XRSTORS instructions */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 11 */
#define X86_FEATURE_PREFETCHWT1 (11*32+ 0) /* PREFETCHWT1 Intel® Xeon PhiTM only */
#define X86_FEATURE_AVX512VBMI (11*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
#define X86_FEATURE_UMIP (11*32+ 2) /* User Mode Instruction Protection */
#define X86_FEATURE_PKU (11*32+ 3) /* Protection Keys for Userspace */
#define X86_FEATURE_OSPKE (11*32+ 4) /* OS Protection Keys Enable */
#define X86_FEATURE_AVX512_VBMI2 (11*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
#define X86_FEATURE_GFNI (11*32+ 8) /* Galois Field New Instructions */
#define X86_FEATURE_VAES (11*32+ 9) /* Vector AES */
#define X86_FEATURE_VPCLMULQDQ (11*32+10) /* Carry-Less Multiplication Double Quadword */
#define X86_FEATURE_AVX512_VNNI (11*32+11) /* Vector Neural Network Instructions */
#define X86_FEATURE_AVX512_BITALG (11*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
#define X86_FEATURE_TME (11*32+13) /* Intel Total Memory Encryption */
#define X86_FEATURE_AVX512_VPOPCNTDQ (11*32+14) /* POPCNT for vectors of DW/QW */
#define X86_FEATURE_LA57 (11*32+16) /* 5-level page tables */
#define X86_FEATURE_RDPID (11*32+22) /* RDPID instruction */
#define X86_FEATURE_CLDEMOTE (11*32+25) /* CLDEMOTE instruction */
#define X86_FEATURE_PREFETCHWT1 (11 * 32 + 0) /* PREFETCHWT1 Intel® Xeon PhiTM only */
#define X86_FEATURE_AVX512VBMI (11 * 32 + 1) /* AVX512 Vector Bit Manipulation instructions*/
#define X86_FEATURE_UMIP (11 * 32 + 2) /* User Mode Instruction Protection */
#define X86_FEATURE_PKU (11 * 32 + 3) /* Protection Keys for Userspace */
#define X86_FEATURE_OSPKE (11 * 32 + 4) /* OS Protection Keys Enable */
#define X86_FEATURE_AVX512_VBMI2 (11 * 32 + 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
#define X86_FEATURE_GFNI (11 * 32 + 8) /* Galois Field New Instructions */
#define X86_FEATURE_VAES (11 * 32 + 9) /* Vector AES */
#define X86_FEATURE_VPCLMULQDQ (11 * 32 + 10) /* Carry-Less Multiplication Double Quadword */
#define X86_FEATURE_AVX512_VNNI (11 * 32 + 11) /* Vector Neural Network Instructions */
#define X86_FEATURE_AVX512_BITALG (11 * 32 + 12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
#define X86_FEATURE_TME (11 * 32 + 13) /* Intel Total Memory Encryption */
#define X86_FEATURE_AVX512_VPOPCNTDQ (11 * 32 + 14) /* POPCNT for vectors of DW/QW */
#define X86_FEATURE_LA57 (11 * 32 + 16) /* 5-level page tables */
#define X86_FEATURE_RDPID (11 * 32 + 22) /* RDPID instruction */
#define X86_FEATURE_CLDEMOTE (11 * 32 + 25) /* CLDEMOTE instruction */
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */
#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring */
#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */
#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */
#define X86_FEATURE_CQM_OCCUP_LLC (12 * 32 + 0) /* LLC occupancy monitoring */
#define X86_FEATURE_CQM_MBM_TOTAL (12 * 32 + 1) /* LLC Total MBM monitoring */
#define X86_FEATURE_CQM_MBM_LOCAL (12 * 32 + 2) /* LLC Local MBM monitoring */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
#define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
#define X86_FEATURE_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */
#define X86_FEATURE_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
#define X86_FEATURE_CLZERO (13 * 32 + 0) /* CLZERO instruction */
#define X86_FEATURE_IRPERF (13 * 32 + 1) /* Instructions Retired Count */
#define X86_FEATURE_XSAVEERPTR (13 * 32 + 2) /* Always save/restore FP error pointers */
#define X86_FEATURE_IBPB (13 * 32 + 12) /* Indirect Branch Prediction Barrier */
#define X86_FEATURE_IBRS (13 * 32 + 14) /* Indirect Branch Restricted Speculation */
#define X86_FEATURE_STIBP (13 * 32 + 15) /* Single Thread Indirect Branch Predictors */
/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */
#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */
#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */
#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */
#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */
#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
#define X86_FEATURE_HDC (14*32+13) /* HDC base registers present */
#define X86_FEATURE_DTHERM (14 * 32 + 0) /* Digital Thermal Sensor */
#define X86_FEATURE_IDA (14 * 32 + 1) /* Intel Dynamic Acceleration */
#define X86_FEATURE_ARAT (14 * 32 + 2) /* Always Running APIC Timer */
#define X86_FEATURE_PLN (14 * 32 + 4) /* Intel Power Limit Notification */
#define X86_FEATURE_PTS (14 * 32 + 6) /* Intel Package Thermal Status */
#define X86_FEATURE_HWP (14 * 32 + 7) /* Intel Hardware P-states */
#define X86_FEATURE_HWP_NOTIFY (14 * 32 + 8) /* HWP Notification */
#define X86_FEATURE_HWP_ACT_WINDOW (14 * 32 + 9) /* HWP Activity Window */
#define X86_FEATURE_HWP_EPP (14 * 32 + 10) /* HWP Energy Perf. Preference */
#define X86_FEATURE_HWP_PKG_REQ (14 * 32 + 11) /* HWP Package Level Request */
#define X86_FEATURE_HDC (14 * 32 + 13) /* HDC base registers present */
/* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */
#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */
#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */
#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */
#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */
#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
#define X86_FEATURE_NPT (15 * 32 + 0) /* Nested Page Table support */
#define X86_FEATURE_LBRV (15 * 32 + 1) /* LBR Virtualization support */
#define X86_FEATURE_SVML (15 * 32 + 2) /* "svm_lock" SVM locking MSR */
#define X86_FEATURE_NRIPS (15 * 32 + 3) /* "nrip_save" SVM next_rip save */
#define X86_FEATURE_TSCRATEMSR (15 * 32 + 4) /* "tsc_scale" TSC scaling support */
#define X86_FEATURE_VMCBCLEAN (15 * 32 + 5) /* "vmcb_clean" VMCB clean bits support */
#define X86_FEATURE_FLUSHBYASID (15 * 32 + 6) /* flush-by-ASID support */
#define X86_FEATURE_DECODEASSISTS (15 * 32 + 7) /* Decode Assists support */
#define X86_FEATURE_PAUSEFILTER (15 * 32 + 10) /* filtered pause intercept */
#define X86_FEATURE_PFTHRESHOLD (15 * 32 + 12) /* pause filter threshold */
#define X86_FEATURE_AVIC (15 * 32 + 13) /* Virtual Interrupt Controller */
#define X86_FEATURE_V_VMSAVE_VMLOAD (15 * 32 + 15) /* Virtual VMSAVE VMLOAD */
#define X86_FEATURE_VGIF (15 * 32 + 16) /* Virtual GIF */
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 16 */
#define X86_FEATURE_CQM_LLC (16*32+ 1) /* LLC QoS if 1 */
#define X86_FEATURE_CQM_LLC (16 * 32 + 1) /* LLC QoS if 1 */
/* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
#define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */
#define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */
#define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */
#define X86_FEATURE_OVERFLOW_RECOV (17 * 32 + 0) /* MCA overflow recovery support */
#define X86_FEATURE_SUCCOR (17 * 32 + 1) /* Uncorrectable error containment and recovery */
#define X86_FEATURE_SMCA (17 * 32 + 3) /* Scalable MCA */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
#define X86_FEATURE_AVX512_4VNNIW (18 * 32 + 2) /* AVX-512 Neural Network Instructions */
#define X86_FEATURE_AVX512_4FMAPS (18 * 32 + 3) /* AVX-512 Multiply Accumulation Single precision */
#define X86_FEATURE_PCONFIG (18 * 32 + 18) /* Intel PCONFIG */
#define X86_FEATURE_SPEC_CTRL (18 * 32 + 26) /* "" Speculation Control (IBRS + IBPB) */
#define X86_FEATURE_INTEL_STIBP (18 * 32 + 27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_ARCH_CAPABILITIES (18 * 32 + 29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
#define X86_FEATURE_SPEC_CTRL_SSBD (18 * 32 + 31) /* "" Speculative Store Bypass Disable */
enum {
X86_VENDOR_INTEL = 0,
X86_VENDOR_AMD = 1,
X86_VENDOR_INTEL = 0,
X86_VENDOR_AMD = 1,
X86_VENDOR_MAX
};
struct cpuinfo_x86 {
/* cpu context */
uint8_t x86_family;
uint8_t x86_vendor;
uint8_t x86_model;
uint8_t x86_mask;
uint32_t x86_capability[NCAPINTS];
uint32_t x86_power;
uint32_t extended_cpuid_level;
int cpuid_level;
char x86_vendor_id[16];
char x86_model_id[64];
uint8_t x86_family;
uint8_t x86_vendor;
uint8_t x86_model;
uint8_t x86_mask;
uint32_t x86_capability[NCAPINTS];
uint32_t x86_power;
uint32_t extended_cpuid_level;
int cpuid_level;
char x86_vendor_id[16];
char x86_model_id[64];
/* fpu context */
uint64_t xfeatures_mask;
uint32_t xsave_size_max;
uint32_t xsave_size;
uint32_t xstate_offsets[XFEATURE_MAX];
uint32_t xstate_sizes[XFEATURE_MAX];
uint64_t xfeatures_mask;
uint32_t xsave_size_max;
uint32_t xsave_size;
uint32_t xstate_offsets[XFEATURE_MAX];
uint32_t xstate_sizes[XFEATURE_MAX];
uint32_t xsaves_size;
uint32_t xstate_comp_offsets[XFEATURE_MAX];
uint32_t xstate_comp_sizes[XFEATURE_MAX];
uint32_t xsaves_size;
uint32_t xstate_comp_offsets[XFEATURE_MAX];
uint32_t xstate_comp_sizes[XFEATURE_MAX];
};
typedef struct cpuinfo_x86 compel_cpuinfo_t;

View File

@ -7,27 +7,27 @@
#include <compel/common/compiler.h>
#define FP_MIN_ALIGN_BYTES 64
#define FXSAVE_ALIGN_BYTES 16
#define FP_MIN_ALIGN_BYTES 64
#define FXSAVE_ALIGN_BYTES 16
#define FP_XSTATE_MAGIC1 0x46505853U
#define FP_XSTATE_MAGIC2 0x46505845U
#define FP_XSTATE_MAGIC1 0x46505853U
#define FP_XSTATE_MAGIC2 0x46505845U
#ifndef FP_XSTATE_MAGIC2_SIZE
#define FP_XSTATE_MAGIC2_SIZE sizeof(FP_XSTATE_MAGIC2)
#define FP_XSTATE_MAGIC2_SIZE sizeof(FP_XSTATE_MAGIC2)
#endif
#define XSTATE_FP 0x1
#define XSTATE_SSE 0x2
#define XSTATE_YMM 0x4
#define XSTATE_FP 0x1
#define XSTATE_SSE 0x2
#define XSTATE_YMM 0x4
#define FXSAVE_SIZE 512
#define XSAVE_SIZE 4096
#define FXSAVE_SIZE 512
#define XSAVE_SIZE 4096
#define XSAVE_HDR_SIZE 64
#define XSAVE_HDR_OFFSET FXSAVE_SIZE
#define XSAVE_HDR_SIZE 64
#define XSAVE_HDR_OFFSET FXSAVE_SIZE
#define XSAVE_YMM_SIZE 256
#define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
#define XSAVE_YMM_SIZE 256
#define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
/*
* List of XSAVE features Linux knows about:
@ -52,91 +52,88 @@ enum xfeature {
XFEATURE_MAX,
};
#define XSTATE_CPUID 0x0000000d
#define XSTATE_CPUID 0x0000000d
#define XFEATURE_MASK_FP (1 << XFEATURE_FP)
#define XFEATURE_MASK_SSE (1 << XFEATURE_SSE)
#define XFEATURE_MASK_YMM (1 << XFEATURE_YMM)
#define XFEATURE_MASK_BNDREGS (1 << XFEATURE_BNDREGS)
#define XFEATURE_MASK_BNDCSR (1 << XFEATURE_BNDCSR)
#define XFEATURE_MASK_OPMASK (1 << XFEATURE_OPMASK)
#define XFEATURE_MASK_ZMM_Hi256 (1 << XFEATURE_ZMM_Hi256)
#define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM)
#define XFEATURE_MASK_PT (1 << XFEATURE_PT)
#define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU)
#define XFEATURE_MASK_HDC (1 << XFEATURE_HDC)
#define XFEATURE_MASK_MAX (1 << XFEATURE_MAX)
#define XFEATURE_MASK_FP (1 << XFEATURE_FP)
#define XFEATURE_MASK_SSE (1 << XFEATURE_SSE)
#define XFEATURE_MASK_YMM (1 << XFEATURE_YMM)
#define XFEATURE_MASK_BNDREGS (1 << XFEATURE_BNDREGS)
#define XFEATURE_MASK_BNDCSR (1 << XFEATURE_BNDCSR)
#define XFEATURE_MASK_OPMASK (1 << XFEATURE_OPMASK)
#define XFEATURE_MASK_ZMM_Hi256 (1 << XFEATURE_ZMM_Hi256)
#define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM)
#define XFEATURE_MASK_PT (1 << XFEATURE_PT)
#define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU)
#define XFEATURE_MASK_HDC (1 << XFEATURE_HDC)
#define XFEATURE_MASK_MAX (1 << XFEATURE_MAX)
#define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
#define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM)
#define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
#define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM)
#define FIRST_EXTENDED_XFEATURE XFEATURE_YMM
#define FIRST_EXTENDED_XFEATURE XFEATURE_YMM
/* Supervisor features */
#define XFEATURE_MASK_SUPERVISOR (XFEATURE_MASK_PT | XFEATURE_HDC)
#define XFEATURE_MASK_SUPERVISOR (XFEATURE_MASK_PT | XFEATURE_HDC)
/* All currently supported features */
#define XFEATURE_MASK_USER \
(XFEATURE_MASK_FP | XFEATURE_MASK_SSE | \
XFEATURE_MASK_YMM | XFEATURE_MASK_OPMASK | \
XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM | \
XFEATURE_MASK_PKRU | XFEATURE_MASK_BNDREGS | \
XFEATURE_MASK_BNDCSR)
#define XFEATURE_MASK_USER \
(XFEATURE_MASK_FP | XFEATURE_MASK_SSE | XFEATURE_MASK_YMM | XFEATURE_MASK_OPMASK | XFEATURE_MASK_ZMM_Hi256 | \
XFEATURE_MASK_Hi16_ZMM | XFEATURE_MASK_PKRU | XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)
struct fpx_sw_bytes {
uint32_t magic1;
uint32_t extended_size;
uint64_t xstate_bv;
uint32_t xstate_size;
uint32_t padding[7];
uint32_t magic1;
uint32_t extended_size;
uint64_t xstate_bv;
uint32_t xstate_size;
uint32_t padding[7];
};
struct i387_fxsave_struct {
uint16_t cwd; /* Control Word */
uint16_t swd; /* Status Word */
uint16_t twd; /* Tag Word */
uint16_t fop; /* Last Instruction Opcode */
uint16_t cwd; /* Control Word */
uint16_t swd; /* Status Word */
uint16_t twd; /* Tag Word */
uint16_t fop; /* Last Instruction Opcode */
union {
struct {
uint64_t rip; /* Instruction Pointer */
uint64_t rdp; /* Data Pointer */
uint64_t rip; /* Instruction Pointer */
uint64_t rdp; /* Data Pointer */
};
struct {
uint32_t fip; /* FPU IP Offset */
uint32_t fcs; /* FPU IP Selector */
uint32_t foo; /* FPU Operand Offset */
uint32_t fos; /* FPU Operand Selector */
uint32_t fip; /* FPU IP Offset */
uint32_t fcs; /* FPU IP Selector */
uint32_t foo; /* FPU Operand Offset */
uint32_t fos; /* FPU Operand Selector */
};
};
uint32_t mxcsr; /* MXCSR Register State */
uint32_t mxcsr_mask; /* MXCSR Mask */
uint32_t mxcsr; /* MXCSR Register State */
uint32_t mxcsr_mask; /* MXCSR Mask */
/* 8*16 bytes for each FP-reg = 128 bytes */
uint32_t st_space[32];
uint32_t st_space[32];
/* 16*16 bytes for each XMM-reg = 256 bytes */
uint32_t xmm_space[64];
uint32_t xmm_space[64];
uint32_t padding[12];
uint32_t padding[12];
union {
uint32_t padding1[12];
uint32_t sw_reserved[12];
uint32_t padding1[12];
uint32_t sw_reserved[12];
};
} __aligned(FXSAVE_ALIGN_BYTES);
struct xsave_hdr_struct {
uint64_t xstate_bv;
uint64_t xcomp_bv;
uint64_t reserved[6];
uint64_t xstate_bv;
uint64_t xcomp_bv;
uint64_t reserved[6];
} __packed;
/*
* xstate_header.xcomp_bv[63] indicates that the extended_state_area
* is in compacted format.
*/
#define XCOMP_BV_COMPACTED_FORMAT ((uint64_t)1 << 63)
#define XCOMP_BV_COMPACTED_FORMAT ((uint64_t)1 << 63)
/*
* State component 2:
@ -149,21 +146,21 @@ struct xsave_hdr_struct {
* The high 128 bits are stored here.
*/
struct ymmh_struct {
uint32_t ymmh_space[64];
uint32_t ymmh_space[64];
} __packed;
/* Intel MPX support: */
struct mpx_bndreg {
uint64_t lower_bound;
uint64_t upper_bound;
uint64_t lower_bound;
uint64_t upper_bound;
} __packed;
/*
* State component 3 is used for the 4 128-bit bounds registers
*/
struct mpx_bndreg_state {
struct mpx_bndreg bndreg[4];
struct mpx_bndreg bndreg[4];
} __packed;
/*
@ -172,8 +169,8 @@ struct mpx_bndreg_state {
* register BNDSTATUS. We call the pair "BNDCSR".
*/
struct mpx_bndcsr {
uint64_t bndcfgu;
uint64_t bndstatus;
uint64_t bndcfgu;
uint64_t bndstatus;
} __packed;
/*
@ -181,8 +178,8 @@ struct mpx_bndcsr {
*/
struct mpx_bndcsr_state {
union {
struct mpx_bndcsr bndcsr;
uint8_t pad_to_64_bytes[64];
struct mpx_bndcsr bndcsr;
uint8_t pad_to_64_bytes[64];
};
} __packed;
@ -193,7 +190,7 @@ struct mpx_bndcsr_state {
* k0-k7 (opmask state).
*/
struct avx_512_opmask_state {
uint64_t opmask_reg[8];
uint64_t opmask_reg[8];
} __packed;
/*
@ -202,7 +199,7 @@ struct avx_512_opmask_state {
* ZMM0_H-ZMM15_H (ZMM_Hi256 state).
*/
struct avx_512_zmm_uppers_state {
uint64_t zmm_upper[16 * 4];
uint64_t zmm_upper[16 * 4];
} __packed;
/*
@ -210,7 +207,7 @@ struct avx_512_zmm_uppers_state {
* ZMM16-ZMM31 (Hi16_ZMM state).
*/
struct avx_512_hi16_state {
uint64_t hi16_zmm[16 * 8];
uint64_t hi16_zmm[16 * 8];
} __packed;
/*
@ -218,8 +215,8 @@ struct avx_512_hi16_state {
* 8 bytes long but only 4 bytes is used currently.
*/
struct pkru_state {
uint32_t pkru;
uint32_t pad;
uint32_t pkru;
uint32_t pad;
} __packed;
/*
@ -234,34 +231,34 @@ struct pkru_state {
*
* One page should be enough for the whole xsave state ;-)
*/
#define EXTENDED_STATE_AREA_SIZE (4096 - sizeof(struct i387_fxsave_struct) - sizeof(struct xsave_hdr_struct))
#define EXTENDED_STATE_AREA_SIZE (4096 - sizeof(struct i387_fxsave_struct) - sizeof(struct xsave_hdr_struct))
/*
* cpu requires it to be 64 byte aligned
*/
struct xsave_struct {
struct i387_fxsave_struct i387;
struct xsave_hdr_struct xsave_hdr;
struct i387_fxsave_struct i387;
struct xsave_hdr_struct xsave_hdr;
union {
/*
* This ymmh is unndeed, for
* backward compatibility.
*/
struct ymmh_struct ymmh;
uint8_t extended_state_area[EXTENDED_STATE_AREA_SIZE];
struct ymmh_struct ymmh;
uint8_t extended_state_area[EXTENDED_STATE_AREA_SIZE];
};
} __aligned(FP_MIN_ALIGN_BYTES) __packed;
struct xsave_struct_ia32 {
struct i387_fxsave_struct i387;
struct xsave_hdr_struct xsave_hdr;
struct i387_fxsave_struct i387;
struct xsave_hdr_struct xsave_hdr;
union {
/*
* This ymmh is unndeed, for
* backward compatibility.
*/
struct ymmh_struct ymmh;
uint8_t extended_state_area[EXTENDED_STATE_AREA_SIZE];
struct ymmh_struct ymmh;
uint8_t extended_state_area[EXTENDED_STATE_AREA_SIZE];
};
};
@ -272,34 +269,34 @@ typedef struct {
*/
union {
struct xsave_struct xsave;
uint8_t __pad[sizeof(struct xsave_struct) + FP_XSTATE_MAGIC2_SIZE];
struct xsave_struct xsave;
uint8_t __pad[sizeof(struct xsave_struct) + FP_XSTATE_MAGIC2_SIZE];
};
uint8_t has_fpu;
} fpu_state_64_t;
struct user_i387_ia32_struct {
uint32_t cwd; /* FPU Control Word */
uint32_t swd; /* FPU Status Word */
uint32_t twd; /* FPU Tag Word */
uint32_t fip; /* FPU IP Offset */
uint32_t fcs; /* FPU IP Selector */
uint32_t foo; /* FPU Operand Pointer Offset */
uint32_t fos; /* FPU Operand Pointer Selector */
uint32_t st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
uint32_t cwd; /* FPU Control Word */
uint32_t swd; /* FPU Status Word */
uint32_t twd; /* FPU Tag Word */
uint32_t fip; /* FPU IP Offset */
uint32_t fcs; /* FPU IP Selector */
uint32_t foo; /* FPU Operand Pointer Offset */
uint32_t fos; /* FPU Operand Pointer Selector */
uint32_t st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
};
typedef struct {
struct {
struct user_i387_ia32_struct i387_ia32;
struct user_i387_ia32_struct i387_ia32;
/* Software status information [not touched by FSAVE]: */
uint32_t status;
uint32_t status;
} fregs_state;
union {
struct xsave_struct_ia32 xsave;
uint8_t __pad[sizeof(struct xsave_struct) + FP_XSTATE_MAGIC2_SIZE];
struct xsave_struct_ia32 xsave;
uint8_t __pad[sizeof(struct xsave_struct) + FP_XSTATE_MAGIC2_SIZE];
} __aligned(FXSAVE_ALIGN_BYTES);
} __aligned(FXSAVE_ALIGN_BYTES) fpu_state_ia32_t;
@ -308,18 +305,17 @@ typedef struct {
*/
typedef struct {
union {
fpu_state_64_t fpu_state_64;
fpu_state_64_t fpu_state_64;
struct {
/* fpu_state_ia32->xsave has to be 64-byte aligned. */
uint32_t __pad[2];
fpu_state_ia32_t fpu_state_ia32;
uint32_t __pad[2];
fpu_state_ia32_t fpu_state_ia32;
};
};
uint8_t has_fpu;
} fpu_state_t;
extern void compel_convert_from_fxsr(struct user_i387_ia32_struct *env,
struct i387_fxsave_struct *fxsave);
extern void compel_convert_from_fxsr(struct user_i387_ia32_struct *env, struct i387_fxsave_struct *fxsave);
#endif /* __CR_ASM_FPU_H__ */

View File

@ -6,8 +6,8 @@
#include <signal.h>
#include <compel/plugins/std/asm/syscall-types.h>
#define SIGMAX 64
#define SIGMAX_OLD 31
#define SIGMAX 64
#define SIGMAX_OLD 31
#define ARCH_HAS_PTRACE_GET_THREAD_AREA
@ -17,11 +17,11 @@
* For 64-bit x86 those GDT offsets are the same
* for native and compat tasks.
*/
#define GDT_ENTRY_TLS_MIN 12
#define GDT_ENTRY_TLS_MAX 14
#define GDT_ENTRY_TLS_NUM 3
#define GDT_ENTRY_TLS_MIN 12
#define GDT_ENTRY_TLS_MAX 14
#define GDT_ENTRY_TLS_NUM 3
typedef struct {
user_desc_t desc[GDT_ENTRY_TLS_NUM];
user_desc_t desc[GDT_ENTRY_TLS_NUM];
} tls_t;
struct thread_ctx;
@ -33,53 +33,53 @@ extern void compel_arch_get_tls_thread(struct parasite_thread_ctl *tctl, tls_t *
extern void compel_arch_get_tls_task(struct parasite_ctl *ctl, tls_t *out);
typedef struct {
uint64_t r15;
uint64_t r14;
uint64_t r13;
uint64_t r12;
uint64_t bp;
uint64_t bx;
uint64_t r11;
uint64_t r10;
uint64_t r9;
uint64_t r8;
uint64_t ax;
uint64_t cx;
uint64_t dx;
uint64_t si;
uint64_t di;
uint64_t orig_ax;
uint64_t ip;
uint64_t cs;
uint64_t flags;
uint64_t sp;
uint64_t ss;
uint64_t fs_base;
uint64_t gs_base;
uint64_t ds;
uint64_t es;
uint64_t fs;
uint64_t gs;
uint64_t r15;
uint64_t r14;
uint64_t r13;
uint64_t r12;
uint64_t bp;
uint64_t bx;
uint64_t r11;
uint64_t r10;
uint64_t r9;
uint64_t r8;
uint64_t ax;
uint64_t cx;
uint64_t dx;
uint64_t si;
uint64_t di;
uint64_t orig_ax;
uint64_t ip;
uint64_t cs;
uint64_t flags;
uint64_t sp;
uint64_t ss;
uint64_t fs_base;
uint64_t gs_base;
uint64_t ds;
uint64_t es;
uint64_t fs;
uint64_t gs;
} user_regs_struct64;
typedef struct {
uint32_t bx;
uint32_t cx;
uint32_t dx;
uint32_t si;
uint32_t di;
uint32_t bp;
uint32_t ax;
uint32_t ds;
uint32_t es;
uint32_t fs;
uint32_t gs;
uint32_t orig_ax;
uint32_t ip;
uint32_t cs;
uint32_t flags;
uint32_t sp;
uint32_t ss;
uint32_t bx;
uint32_t cx;
uint32_t dx;
uint32_t si;
uint32_t di;
uint32_t bp;
uint32_t ax;
uint32_t ds;
uint32_t es;
uint32_t fs;
uint32_t gs;
uint32_t orig_ax;
uint32_t ip;
uint32_t cs;
uint32_t flags;
uint32_t sp;
uint32_t ss;
} user_regs_struct32;
/*
@ -96,22 +96,17 @@ typedef struct {
short __is_native; /* use user_regs_native macro to check it */
} user_regs_struct_t;
#define NATIVE_MAGIC 0x0A
#define COMPAT_MAGIC 0x0C
#define NATIVE_MAGIC 0x0A
#define COMPAT_MAGIC 0x0C
static inline bool user_regs_native(user_regs_struct_t *pregs)
{
return pregs->__is_native == NATIVE_MAGIC;
}
#define get_user_reg(pregs, name) \
((user_regs_native(pregs)) ? \
((pregs)->native.name) : \
((pregs)->compat.name))
#define get_user_reg(pregs, name) ((user_regs_native(pregs)) ? ((pregs)->native.name) : ((pregs)->compat.name))
#define set_user_reg(pregs, name, val) \
((user_regs_native(pregs)) ? \
((pregs)->native.name = (val)) : \
((pregs)->compat.name = (val)))
#define set_user_reg(pregs, name, val) \
((user_regs_native(pregs)) ? ((pregs)->native.name = (val)) : ((pregs)->compat.name = (val)))
#if 0
typedef struct {
@ -132,12 +127,12 @@ typedef struct {
typedef struct xsave_struct user_fpregs_struct_t;
#define REG_RES(regs) get_user_reg(&regs, ax)
#define REG_IP(regs) get_user_reg(&regs, ip)
#define REG_SP(regs) get_user_reg(&regs, sp)
#define REG_SYSCALL_NR(regs) get_user_reg(&regs, orig_ax)
#define REG_RES(regs) get_user_reg(&regs, ax)
#define REG_IP(regs) get_user_reg(&regs, ip)
#define REG_SP(regs) get_user_reg(&regs, sp)
#define REG_SYSCALL_NR(regs) get_user_reg(&regs, orig_ax)
#define __NR(syscall, compat) ((compat) ? __NR32_##syscall : __NR_##syscall)
#define __NR(syscall, compat) ((compat) ? __NR32_##syscall : __NR_##syscall)
/*
* For x86_32 __NR_mmap inside the kernel represents old_mmap system

View File

@ -7,7 +7,7 @@
* EFLAGS bits
*/
#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
#define X86_EFLAGS_BIT1 0x00000002 /* Bit 1 - always on */
#define X86_EFLAGS_BIT1 0x00000002 /* Bit 1 - always on */
#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
#define X86_EFLAGS_AF 0x00000010 /* Auxiliary carry Flag */
#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
@ -16,7 +16,7 @@
#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */

View File

@ -11,60 +11,60 @@
#define SIGFRAME_MAX_OFFSET 8
struct rt_sigcontext {
uint64_t r8;
uint64_t r9;
uint64_t r10;
uint64_t r11;
uint64_t r12;
uint64_t r13;
uint64_t r14;
uint64_t r15;
uint64_t rdi;
uint64_t rsi;
uint64_t rbp;
uint64_t rbx;
uint64_t rdx;
uint64_t rax;
uint64_t rcx;
uint64_t rsp;
uint64_t rip;
uint64_t eflags;
uint16_t cs;
uint16_t gs;
uint16_t fs;
uint16_t ss;
uint64_t err;
uint64_t trapno;
uint64_t oldmask;
uint64_t cr2;
uint64_t fpstate;
uint64_t reserved1[8];
uint64_t r8;
uint64_t r9;
uint64_t r10;
uint64_t r11;
uint64_t r12;
uint64_t r13;
uint64_t r14;
uint64_t r15;
uint64_t rdi;
uint64_t rsi;
uint64_t rbp;
uint64_t rbx;
uint64_t rdx;
uint64_t rax;
uint64_t rcx;
uint64_t rsp;
uint64_t rip;
uint64_t eflags;
uint16_t cs;
uint16_t gs;
uint16_t fs;
uint16_t ss;
uint64_t err;
uint64_t trapno;
uint64_t oldmask;
uint64_t cr2;
uint64_t fpstate;
uint64_t reserved1[8];
};
struct rt_sigcontext_32 {
uint32_t gs;
uint32_t fs;
uint32_t es;
uint32_t ds;
uint32_t di;
uint32_t si;
uint32_t bp;
uint32_t sp;
uint32_t bx;
uint32_t dx;
uint32_t cx;
uint32_t ax;
uint32_t trapno;
uint32_t err;
uint32_t ip;
uint32_t cs;
uint32_t flags;
uint32_t sp_at_signal;
uint32_t ss;
uint32_t gs;
uint32_t fs;
uint32_t es;
uint32_t ds;
uint32_t di;
uint32_t si;
uint32_t bp;
uint32_t sp;
uint32_t bx;
uint32_t dx;
uint32_t cx;
uint32_t ax;
uint32_t trapno;
uint32_t err;
uint32_t ip;
uint32_t cs;
uint32_t flags;
uint32_t sp_at_signal;
uint32_t ss;
uint32_t fpstate;
uint32_t oldmask;
uint32_t cr2;
uint32_t fpstate;
uint32_t oldmask;
uint32_t cr2;
};
#include <compel/sigframe-common.h>
@ -74,71 +74,70 @@ struct rt_sigcontext_32 {
* when (if) other architectures will support compatible C/R
*/
typedef uint32_t compat_uptr_t;
typedef uint32_t compat_size_t;
typedef uint32_t compat_sigset_word;
typedef uint32_t compat_uptr_t;
typedef uint32_t compat_size_t;
typedef uint32_t compat_sigset_word;
typedef struct compat_siginfo {
int si_signo;
int si_errno;
int si_code;
int _pad[128/sizeof(int) - 3];
int si_signo;
int si_errno;
int si_code;
int _pad[128 / sizeof(int) - 3];
} compat_siginfo_t;
typedef struct compat_sigaltstack {
compat_uptr_t ss_sp;
int ss_flags;
compat_size_t ss_size;
compat_uptr_t ss_sp;
int ss_flags;
compat_size_t ss_size;
} compat_stack_t;
#define _COMPAT_NSIG 64
#define _COMPAT_NSIG_BPW 32
#define _COMPAT_NSIG_WORDS (_COMPAT_NSIG / _COMPAT_NSIG_BPW)
#define _COMPAT_NSIG 64
#define _COMPAT_NSIG_BPW 32
#define _COMPAT_NSIG_WORDS (_COMPAT_NSIG / _COMPAT_NSIG_BPW)
typedef struct {
compat_sigset_word sig[_COMPAT_NSIG_WORDS];
compat_sigset_word sig[_COMPAT_NSIG_WORDS];
} compat_sigset_t;
struct ucontext_ia32 {
unsigned int uc_flags;
unsigned int uc_link;
compat_stack_t uc_stack;
struct rt_sigcontext_32 uc_mcontext;
compat_sigset_t uc_sigmask; /* mask last for extensibility */
unsigned int uc_flags;
unsigned int uc_link;
compat_stack_t uc_stack;
struct rt_sigcontext_32 uc_mcontext;
compat_sigset_t uc_sigmask; /* mask last for extensibility */
};
struct rt_sigframe_ia32 {
uint32_t pretcode;
int32_t sig;
uint32_t pinfo;
uint32_t puc;
compat_siginfo_t info;
struct ucontext_ia32 uc;
char retcode[8];
uint32_t pretcode;
int32_t sig;
uint32_t pinfo;
uint32_t puc;
compat_siginfo_t info;
struct ucontext_ia32 uc;
char retcode[8];
/* fp state follows here */
fpu_state_t fpu_state;
fpu_state_t fpu_state;
};
struct rt_sigframe_64 {
char *pretcode;
struct rt_ucontext uc;
struct rt_siginfo info;
char *pretcode;
struct rt_ucontext uc;
struct rt_siginfo info;
/* fp state follows here */
fpu_state_t fpu_state;
fpu_state_t fpu_state;
};
struct rt_sigframe {
union {
struct rt_sigframe_ia32 compat;
struct rt_sigframe_64 native;
struct rt_sigframe_ia32 compat;
struct rt_sigframe_64 native;
};
bool is_native;
};
static inline
void rt_sigframe_copy_sigset(struct rt_sigframe *to, k_rtsigset_t *from)
static inline void rt_sigframe_copy_sigset(struct rt_sigframe *to, k_rtsigset_t *from)
{
size_t sz = sizeof(k_rtsigset_t);
@ -149,8 +148,7 @@ void rt_sigframe_copy_sigset(struct rt_sigframe *to, k_rtsigset_t *from)
memcpy(&to->compat.uc.uc_sigmask, from, sz);
}
static inline
void rt_sigframe_erase_sigset(struct rt_sigframe *sigframe)
static inline void rt_sigframe_erase_sigset(struct rt_sigframe *sigframe)
{
size_t sz = sizeof(k_rtsigset_t);
@ -160,15 +158,11 @@ void rt_sigframe_erase_sigset(struct rt_sigframe *sigframe)
memset(&sigframe->compat.uc.uc_sigmask, 0, sz);
}
#define RT_SIGFRAME_REGIP(rt_sigframe) \
((rt_sigframe->is_native) ? \
(rt_sigframe)->native.uc.uc_mcontext.rip : \
(rt_sigframe)->compat.uc.uc_mcontext.ip)
#define RT_SIGFRAME_REGIP(rt_sigframe) \
((rt_sigframe->is_native) ? (rt_sigframe)->native.uc.uc_mcontext.rip : (rt_sigframe)->compat.uc.uc_mcontext.ip)
#define RT_SIGFRAME_FPU(rt_sigframe) \
((rt_sigframe->is_native) ? \
(&(rt_sigframe)->native.fpu_state) : \
(&(rt_sigframe)->compat.fpu_state))
#define RT_SIGFRAME_FPU(rt_sigframe) \
((rt_sigframe->is_native) ? (&(rt_sigframe)->native.fpu_state) : (&(rt_sigframe)->compat.fpu_state))
#define RT_SIGFRAME_HAS_FPU(rt_sigframe) (RT_SIGFRAME_FPU(rt_sigframe)->has_fpu)
@ -178,10 +172,11 @@ void rt_sigframe_erase_sigset(struct rt_sigframe *sigframe)
* - compatible is in sys32_rt_sigreturn at arch/x86/ia32/ia32_signal.c
* - native is in sys_rt_sigreturn at arch/x86/kernel/signal.c
*/
#define RT_SIGFRAME_OFFSET(rt_sigframe) (((rt_sigframe)->is_native) ? 8 : 4 )
#define RT_SIGFRAME_OFFSET(rt_sigframe) (((rt_sigframe)->is_native) ? 8 : 4)
#define USER32_CS 0x23
#define USER32_CS 0x23
/* clang-format off */
#define ARCH_RT_SIGRETURN_NATIVE(new_sp) \
asm volatile( \
"movq %0, %%rax \n" \
@ -215,6 +210,7 @@ do { \
else \
ARCH_RT_SIGRETURN_COMPAT(new_sp); \
} while (0)
/* clang-format off */
int sigreturn_prep_fpu_frame(struct rt_sigframe *sigframe,
struct rt_sigframe *rsigframe);

View File

@ -1,16 +1,16 @@
#ifndef COMPEL_ELF32_TYPES_H__
#define COMPEL_ELF32_TYPES_H__
#define Elf_Ehdr Elf32_Ehdr
#define Elf_Shdr Elf32_Shdr
#define Elf_Sym Elf32_Sym
#define Elf_Rel Elf32_Rel
#define Elf_Rela Elf32_Rela
#define Elf_Ehdr Elf32_Ehdr
#define Elf_Shdr Elf32_Shdr
#define Elf_Sym Elf32_Sym
#define Elf_Rel Elf32_Rel
#define Elf_Rela Elf32_Rela
#define ELF_ST_TYPE ELF32_ST_TYPE
#define ELF_ST_BIND ELF32_ST_BIND
#define ELF_ST_TYPE ELF32_ST_TYPE
#define ELF_ST_BIND ELF32_ST_BIND
#define ELF_R_SYM ELF32_R_SYM
#define ELF_R_TYPE ELF32_R_TYPE
#define ELF_R_SYM ELF32_R_SYM
#define ELF_R_TYPE ELF32_R_TYPE
#endif /* COMPEL_ELF32_TYPES_H__ */

View File

@ -1,16 +1,16 @@
#ifndef COMPEL_ELF64_TYPES_H__
#define COMPEL_ELF64_TYPES_H__
#define Elf_Ehdr Elf64_Ehdr
#define Elf_Shdr Elf64_Shdr
#define Elf_Sym Elf64_Sym
#define Elf_Rel Elf64_Rel
#define Elf_Rela Elf64_Rela
#define Elf_Ehdr Elf64_Ehdr
#define Elf_Shdr Elf64_Shdr
#define Elf_Sym Elf64_Sym
#define Elf_Rel Elf64_Rel
#define Elf_Rela Elf64_Rela
#define ELF_ST_TYPE ELF64_ST_TYPE
#define ELF_ST_BIND ELF64_ST_BIND
#define ELF_ST_TYPE ELF64_ST_TYPE
#define ELF_ST_BIND ELF64_ST_BIND
#define ELF_R_SYM ELF64_R_SYM
#define ELF_R_TYPE ELF64_R_TYPE
#define ELF_R_SYM ELF64_R_SYM
#define ELF_R_TYPE ELF64_R_TYPE
#endif /* COMPEL_ELF64_TYPES_H__ */

View File

@ -1,9 +1,9 @@
#ifndef __COMPEL_ERRNO_H__
#define __COMPEL_ERRNO_H__
#define ERESTARTSYS 512
#define ERESTARTNOINTR 513
#define ERESTARTNOHAND 514
#define ERESTART_RESTARTBLOCK 516
#define ERESTARTSYS 512
#define ERESTARTNOINTR 513
#define ERESTARTNOHAND 514
#define ERESTART_RESTARTBLOCK 516
#endif /* __CR_ERRNO_H__ */

View File

@ -3,64 +3,63 @@
#include <stdbool.h>
#define BUILTIN_SYSCALL_SIZE 8
#define BUILTIN_SYSCALL_SIZE 8
struct thread_ctx {
k_rtsigset_t sigmask;
user_regs_struct_t regs;
k_rtsigset_t sigmask;
user_regs_struct_t regs;
#ifdef ARCH_HAS_PTRACE_GET_THREAD_AREA
tls_t tls;
tls_t tls;
#endif
user_fpregs_struct_t ext_regs;
user_fpregs_struct_t ext_regs;
};
/* parasite control block */
struct parasite_ctl {
int rpid; /* Real pid of the victim */
void *remote_map;
void *local_map;
void *sigreturn_addr; /* A place for the breakpoint */
unsigned long map_length;
int rpid; /* Real pid of the victim */
void *remote_map;
void *local_map;
void *sigreturn_addr; /* A place for the breakpoint */
unsigned long map_length;
struct infect_ctx ictx;
struct infect_ctx ictx;
/* thread leader data */
bool daemonized;
bool daemonized;
struct thread_ctx orig;
struct thread_ctx orig;
void *rstack; /* thread leader stack*/
struct rt_sigframe *sigframe;
struct rt_sigframe *rsigframe; /* address in a parasite */
void *rstack; /* thread leader stack*/
struct rt_sigframe *sigframe;
struct rt_sigframe *rsigframe; /* address in a parasite */
void *r_thread_stack; /* stack for non-leader threads */
void *r_thread_stack; /* stack for non-leader threads */
unsigned long parasite_ip; /* service routine start ip */
unsigned long parasite_ip; /* service routine start ip */
unsigned int *cmd; /* address for command */
void *args; /* address for arguments */
unsigned long args_size;
int tsock; /* transport socket for transferring fds */
unsigned int *cmd; /* address for command */
void *args; /* address for arguments */
unsigned long args_size;
int tsock; /* transport socket for transferring fds */
struct parasite_blob_desc pblob;
};
struct parasite_thread_ctl {
int tid;
struct parasite_ctl *ctl;
struct thread_ctx th;
int tid;
struct parasite_ctl *ctl;
struct thread_ctx th;
};
#define MEMFD_FNAME "CRIUMFD"
#define MEMFD_FNAME_SZ sizeof(MEMFD_FNAME)
#define MEMFD_FNAME "CRIUMFD"
#define MEMFD_FNAME_SZ sizeof(MEMFD_FNAME)
struct ctl_msg;
int parasite_wait_ack(int sockfd, unsigned int cmd, struct ctl_msg *m);
extern void parasite_setup_regs(unsigned long new_ip, void *stack, user_regs_struct_t *regs);
extern void *remote_mmap(struct parasite_ctl *ctl,
void *addr, size_t length, int prot,
int flags, int fd, off_t offset);
extern void *remote_mmap(struct parasite_ctl *ctl, void *addr, size_t length, int prot, int flags, int fd,
off_t offset);
extern bool arch_can_dump_task(struct parasite_ctl *ctl);
/*
* @regs: general purpose registers
@ -70,16 +69,12 @@ extern bool arch_can_dump_task(struct parasite_ctl *ctl);
* @flags: see INFECT_* in infect_ctx::flags
* @pid: mystery
*/
extern int compel_get_task_regs(pid_t pid, user_regs_struct_t *regs,
user_fpregs_struct_t *ext_regs, save_regs_t save,
void *arg, unsigned long flags);
extern int compel_get_task_regs(pid_t pid, user_regs_struct_t *regs, user_fpregs_struct_t *ext_regs, save_regs_t save,
void *arg, unsigned long flags);
extern int compel_set_task_ext_regs(pid_t pid, user_fpregs_struct_t *ext_regs);
extern int arch_fetch_sas(struct parasite_ctl *ctl, struct rt_sigframe *s);
extern int sigreturn_prep_regs_plain(struct rt_sigframe *sigframe,
user_regs_struct_t *regs,
extern int sigreturn_prep_regs_plain(struct rt_sigframe *sigframe, user_regs_struct_t *regs,
user_fpregs_struct_t *fpregs);
extern int sigreturn_prep_fpu_frame_plain(struct rt_sigframe *sigframe,
struct rt_sigframe *rsigframe);
extern int compel_execute_syscall(struct parasite_ctl *ctl,
user_regs_struct_t *regs, const char *code_syscall);
extern int sigreturn_prep_fpu_frame_plain(struct rt_sigframe *sigframe, struct rt_sigframe *rsigframe);
extern int compel_execute_syscall(struct parasite_ctl *ctl, user_regs_struct_t *regs, const char *code_syscall);
#endif

View File

@ -4,60 +4,47 @@
#include "uapi/compel/log.h"
#ifndef LOG_PREFIX
# define LOG_PREFIX
#define LOG_PREFIX
#endif
static inline int pr_quelled(unsigned int loglevel)
{
return compel_log_get_loglevel() < loglevel
&& loglevel != COMPEL_LOG_MSG;
return compel_log_get_loglevel() < loglevel && loglevel != COMPEL_LOG_MSG;
}
extern void compel_print_on_level(unsigned int loglevel,
const char *format, ...)
__attribute__ ((__format__ (__printf__, 2, 3)));
extern void compel_print_on_level(unsigned int loglevel, const char *format, ...)
__attribute__((__format__(__printf__, 2, 3)));
#define pr_msg(fmt, ...) \
compel_print_on_level(COMPEL_LOG_MSG, \
fmt, ##__VA_ARGS__)
#define pr_msg(fmt, ...) compel_print_on_level(COMPEL_LOG_MSG, fmt, ##__VA_ARGS__)
#define pr_info(fmt, ...) \
compel_print_on_level(COMPEL_LOG_INFO, \
LOG_PREFIX fmt, ##__VA_ARGS__)
#define pr_info(fmt, ...) compel_print_on_level(COMPEL_LOG_INFO, LOG_PREFIX fmt, ##__VA_ARGS__)
#define pr_err(fmt, ...) \
compel_print_on_level(COMPEL_LOG_ERROR, \
"Error (%s:%d): " LOG_PREFIX fmt, \
__FILE__, __LINE__, ##__VA_ARGS__)
#define pr_err(fmt, ...) \
compel_print_on_level(COMPEL_LOG_ERROR, "Error (%s:%d): " LOG_PREFIX fmt, __FILE__, __LINE__, ##__VA_ARGS__)
#define pr_err_once(fmt, ...) \
do { \
static bool __printed; \
if (!__printed) { \
pr_err(fmt, ##__VA_ARGS__); \
__printed = 1; \
} \
#define pr_err_once(fmt, ...) \
do { \
static bool __printed; \
if (!__printed) { \
pr_err(fmt, ##__VA_ARGS__); \
__printed = 1; \
} \
} while (0)
#define pr_warn(fmt, ...) \
compel_print_on_level(COMPEL_LOG_WARN, \
"Warn (%s:%d): " LOG_PREFIX fmt, \
__FILE__, __LINE__, ##__VA_ARGS__)
#define pr_warn(fmt, ...) \
compel_print_on_level(COMPEL_LOG_WARN, "Warn (%s:%d): " LOG_PREFIX fmt, __FILE__, __LINE__, ##__VA_ARGS__)
#define pr_warn_once(fmt, ...) \
do { \
static bool __printed; \
if (!__printed) { \
pr_warn(fmt, ##__VA_ARGS__); \
__printed = 1; \
} \
#define pr_warn_once(fmt, ...) \
do { \
static bool __printed; \
if (!__printed) { \
pr_warn(fmt, ##__VA_ARGS__); \
__printed = 1; \
} \
} while (0)
#define pr_debug(fmt, ...) \
compel_print_on_level(COMPEL_LOG_DEBUG, \
LOG_PREFIX fmt, ##__VA_ARGS__)
#define pr_debug(fmt, ...) compel_print_on_level(COMPEL_LOG_DEBUG, LOG_PREFIX fmt, ##__VA_ARGS__)
#define pr_perror(fmt, ...) \
pr_err(fmt ": %m\n", ##__VA_ARGS__)
#define pr_perror(fmt, ...) pr_err(fmt ": %m\n", ##__VA_ARGS__)
#endif /* COMPEL_LOG_H__ */

View File

@ -9,19 +9,19 @@
#include "common/compiler.h"
typedef struct {
char *input_filename;
char *output_filename;
char *prefix;
FILE *fout;
char *input_filename;
char *output_filename;
char *prefix;
FILE *fout;
} piegen_opt_t;
extern piegen_opt_t opts;
#define pr_out(fmt, ...) \
do { \
if (opts.fout) \
fprintf(opts.fout, fmt, ##__VA_ARGS__); \
} while (0)
#define pr_out(fmt, ...) \
do { \
if (opts.fout) \
fprintf(opts.fout, fmt, ##__VA_ARGS__); \
} while (0)
extern int handle_binary(void *mem, size_t size);

View File

@ -5,7 +5,7 @@
#include <compel/asm/infect-types.h>
#include <compel/ptrace.h>
#define PTRACE_SI_EVENT(_si_code) (((_si_code) & 0xFFFF) >> 8)
#define PTRACE_SI_EVENT(_si_code) (((_si_code)&0xFFFF) >> 8)
extern int ptrace_get_regs(pid_t pid, user_regs_struct_t *regs);
extern int ptrace_set_regs(pid_t pid, user_regs_struct_t *regs);

View File

@ -1,16 +1,22 @@
#ifndef __COMPEL_RPC_H__
#define __COMPEL_RPC_H__
struct ctl_msg {
uint32_t cmd; /* command itself */
uint32_t ack; /* ack on command */
int32_t err; /* error code on reply */
uint32_t cmd; /* command itself */
uint32_t ack; /* ack on command */
int32_t err; /* error code on reply */
};
#define ctl_msg_cmd(_cmd) \
(struct ctl_msg){.cmd = _cmd, }
#define ctl_msg_cmd(_cmd) \
(struct ctl_msg) \
{ \
.cmd = _cmd, \
}
#define ctl_msg_ack(_cmd, _err) \
(struct ctl_msg){.cmd = _cmd, .ack = _cmd, .err = _err, }
#define ctl_msg_ack(_cmd, _err) \
(struct ctl_msg) \
{ \
.cmd = _cmd, .ack = _cmd, .err = _err, \
}
/*
* NOTE: each command's args should be arch-independed sized.
@ -18,7 +24,7 @@ struct ctl_msg {
* alternative type for compatible tasks in parasite-compat.h
*/
enum {
PARASITE_CMD_IDLE = 0,
PARASITE_CMD_IDLE = 0,
PARASITE_CMD_ACK,
PARASITE_CMD_INIT_DAEMON,
@ -32,19 +38,19 @@ enum {
};
struct parasite_init_args {
int32_t h_addr_len;
struct sockaddr_un h_addr;
int32_t log_level;
uint64_t sigreturn_addr;
uint64_t sigframe; /* pointer to sigframe */
futex_t daemon_connected;
int32_t h_addr_len;
struct sockaddr_un h_addr;
int32_t log_level;
uint64_t sigreturn_addr;
uint64_t sigframe; /* pointer to sigframe */
futex_t daemon_connected;
#ifdef ARCH_HAS_LONG_PAGES
uint32_t page_size;
uint32_t page_size;
#endif
};
struct parasite_unmap_args {
uint64_t parasite_start;
uint64_t parasite_len;
uint64_t parasite_start;
uint64_t parasite_len;
};
#endif

View File

@ -7,4 +7,3 @@ struct shmem_plugin_msg {
};
#endif /* __COMPEL_PLUGIN_SHMEM_PRIV_H__ */

View File

@ -1,22 +1,22 @@
#ifndef __COMPEL_UAPI_HANDLE_ELF__
#define __COMPEL_UAPI_HANDLE_ELF__
#define COMPEL_TYPE_INT (1u << 0)
#define COMPEL_TYPE_LONG (1u << 1)
#define COMPEL_TYPE_GOTPCREL (1u << 2)
#define COMPEL_TYPE_INT (1u << 0)
#define COMPEL_TYPE_LONG (1u << 1)
#define COMPEL_TYPE_GOTPCREL (1u << 2)
#ifdef CONFIG_MIPS
#define COMPEL_TYPE_MIPS_26 (1u << 3)
#define COMPEL_TYPE_MIPS_HI16 (1u << 4)
#define COMPEL_TYPE_MIPS_LO16 (1u << 5)
#define COMPEL_TYPE_MIPS_HIGHER (1u << 6)
#define COMPEL_TYPE_MIPS_HIGHEST (1u << 7)
#define COMPEL_TYPE_MIPS_64 (1u << 8)
#define COMPEL_TYPE_MIPS_26 (1u << 3)
#define COMPEL_TYPE_MIPS_HI16 (1u << 4)
#define COMPEL_TYPE_MIPS_LO16 (1u << 5)
#define COMPEL_TYPE_MIPS_HIGHER (1u << 6)
#define COMPEL_TYPE_MIPS_HIGHEST (1u << 7)
#define COMPEL_TYPE_MIPS_64 (1u << 8)
#endif
typedef struct {
unsigned int offset;
unsigned int type;
long addend;
long value;
unsigned int offset;
unsigned int type;
long addend;
long value;
} compel_reloc_t;
#endif

View File

@ -13,7 +13,6 @@ extern int __must_check compel_rpc_call(unsigned int cmd, struct parasite_ctl *c
extern int __must_check compel_rpc_call_sync(unsigned int cmd, struct parasite_ctl *ctl);
extern int compel_rpc_sock(struct parasite_ctl *ctl);
#define PARASITE_USER_CMDS 64
#define PARASITE_USER_CMDS 64
#endif

View File

@ -11,23 +11,23 @@
#include "common/compiler.h"
#define PARASITE_START_AREA_MIN (4096)
#define PARASITE_START_AREA_MIN (4096)
extern int __must_check compel_interrupt_task(int pid);
struct seize_task_status {
unsigned long long sigpnd;
unsigned long long shdpnd;
char state;
int vpid;
int ppid;
int seccomp_mode;
unsigned long long sigpnd;
unsigned long long shdpnd;
char state;
int vpid;
int ppid;
int seccomp_mode;
};
extern int __must_check compel_wait_task(int pid, int ppid,
int (*get_status)(int pid, struct seize_task_status *, void *data),
void (*free_status)(int pid, struct seize_task_status *, void *data),
struct seize_task_status *st, void *data);
int (*get_status)(int pid, struct seize_task_status *, void *data),
void (*free_status)(int pid, struct seize_task_status *, void *data),
struct seize_task_status *st, void *data);
extern int __must_check compel_stop_task(int pid);
extern int compel_resume_task(pid_t pid, int orig_state, int state);
@ -37,8 +37,7 @@ struct parasite_thread_ctl;
extern struct parasite_ctl __must_check *compel_prepare(int pid);
extern struct parasite_ctl __must_check *compel_prepare_noctx(int pid);
extern int __must_check compel_infect(struct parasite_ctl *ctl,
unsigned long nr_threads, unsigned long args_size);
extern int __must_check compel_infect(struct parasite_ctl *ctl, unsigned long nr_threads, unsigned long args_size);
extern struct parasite_thread_ctl __must_check *compel_prepare_thread(struct parasite_ctl *ctl, int pid);
extern void compel_release_thread(struct parasite_thread_ctl *);
@ -47,27 +46,22 @@ extern int __must_check compel_cure_remote(struct parasite_ctl *ctl);
extern int __must_check compel_cure_local(struct parasite_ctl *ctl);
extern int __must_check compel_cure(struct parasite_ctl *ctl);
#define PARASITE_ARG_SIZE_MIN ( 1 << 12)
#define PARASITE_ARG_SIZE_MIN (1 << 12)
#define compel_parasite_args(ctl, type) \
({ \
void *___ret; \
BUILD_BUG_ON(sizeof(type) > PARASITE_ARG_SIZE_MIN); \
___ret = compel_parasite_args_p(ctl); \
___ret; \
#define compel_parasite_args(ctl, type) \
({ \
void *___ret; \
BUILD_BUG_ON(sizeof(type) > PARASITE_ARG_SIZE_MIN); \
___ret = compel_parasite_args_p(ctl); \
___ret; \
})
extern void *compel_parasite_args_p(struct parasite_ctl *ctl);
extern void *compel_parasite_args_s(struct parasite_ctl *ctl, unsigned long args_size);
extern int __must_check compel_syscall(struct parasite_ctl *ctl,
int nr, long *ret,
unsigned long arg1,
unsigned long arg2,
unsigned long arg3,
unsigned long arg4,
unsigned long arg5,
unsigned long arg6);
extern int __must_check compel_syscall(struct parasite_ctl *ctl, int nr, long *ret, unsigned long arg1,
unsigned long arg2, unsigned long arg3, unsigned long arg4, unsigned long arg5,
unsigned long arg6);
extern int __must_check compel_run_in_thread(struct parasite_thread_ctl *tctl, unsigned int cmd);
extern int __must_check compel_run_at(struct parasite_ctl *ctl, unsigned long ip, user_regs_struct_t *ret_regs);
@ -83,11 +77,9 @@ enum trace_flags {
TRACE_EXIT,
};
extern int __must_check compel_stop_on_syscall(int tasks, int sys_nr,
int sys_nr_compat, enum trace_flags trace);
extern int __must_check compel_stop_on_syscall(int tasks, int sys_nr, int sys_nr_compat, enum trace_flags trace);
extern int __must_check compel_stop_pie(pid_t pid, void *addr,
enum trace_flags *tf, bool no_bp);
extern int __must_check compel_stop_pie(pid_t pid, void *addr, enum trace_flags *tf, bool no_bp);
extern int __must_check compel_unmap(struct parasite_ctl *ctl, unsigned long addr);
@ -98,69 +90,68 @@ extern k_rtsigset_t *compel_thread_sigmask(struct parasite_thread_ctl *tctl);
struct rt_sigframe;
typedef int (*open_proc_fn)(int pid, int mode, const char *fmt, ...)
__attribute__ ((__format__ (__printf__, 3, 4)));
typedef int (*open_proc_fn)(int pid, int mode, const char *fmt, ...) __attribute__((__format__(__printf__, 3, 4)));
typedef int (*save_regs_t)(void *, user_regs_struct_t *, user_fpregs_struct_t *);
typedef int (*make_sigframe_t)(void *, struct rt_sigframe *, struct rt_sigframe *, k_rtsigset_t *);
struct infect_ctx {
int sock;
int sock;
/*
* Regs manipulation context.
*/
save_regs_t save_regs;
make_sigframe_t make_sigframe;
save_regs_t save_regs;
make_sigframe_t make_sigframe;
void *regs_arg;
unsigned long task_size;
unsigned long syscall_ip; /* entry point of infection */
unsigned long flags; /* fine-tune (e.g. faults) */
unsigned long task_size;
unsigned long syscall_ip; /* entry point of infection */
unsigned long flags; /* fine-tune (e.g. faults) */
void (*child_handler)(int, siginfo_t *, void *); /* hander for SIGCHLD deaths */
struct sigaction orig_handler;
void (*child_handler)(int, siginfo_t *, void *); /* hander for SIGCHLD deaths */
struct sigaction orig_handler;
open_proc_fn open_proc;
int log_fd; /* fd for parasite code to send messages to */
int log_fd; /* fd for parasite code to send messages to */
};
extern struct infect_ctx *compel_infect_ctx(struct parasite_ctl *);
/* Don't use memfd() */
#define INFECT_NO_MEMFD (1UL << 0)
#define INFECT_NO_MEMFD (1UL << 0)
/* Make parasite connect() fail */
#define INFECT_FAIL_CONNECT (1UL << 1)
#define INFECT_FAIL_CONNECT (1UL << 1)
/* No breakpoints in pie tracking */
#define INFECT_NO_BREAKPOINTS (1UL << 2)
#define INFECT_NO_BREAKPOINTS (1UL << 2)
/* Can run parasite inside compat tasks */
#define INFECT_COMPATIBLE (1UL << 3)
#define INFECT_COMPATIBLE (1UL << 3)
/* Workaround for ptrace bug on Skylake CPUs with kernels older than v4.14 */
#define INFECT_X86_PTRACE_MXCSR_BUG (1UL << 4)
#define INFECT_X86_PTRACE_MXCSR_BUG (1UL << 4)
/* After infecting - corrupt extended registers (fault-injection) */
#define INFECT_CORRUPT_EXTREGS (1UL << 5)
#define INFECT_CORRUPT_EXTREGS (1UL << 5)
/*
* There are several ways to describe a blob to compel
* library. The simplest one derived from criu is to
* provide it from .h files.
*/
#define COMPEL_BLOB_CHEADER 0x1
#define COMPEL_BLOB_CHEADER 0x1
struct parasite_blob_desc {
unsigned parasite_type;
unsigned parasite_type;
union {
struct {
const void *mem;
size_t bsize;
unsigned long parasite_ip_off;
unsigned long cmd_off;
unsigned long args_ptr_off;
unsigned long got_off;
unsigned long args_off;
unsigned long data_off;
compel_reloc_t *relocs;
unsigned int nr_relocs;
const void *mem;
size_t bsize;
unsigned long parasite_ip_off;
unsigned long cmd_off;
unsigned long args_ptr_off;
unsigned long got_off;
unsigned long args_off;
unsigned long data_off;
compel_reloc_t *relocs;
unsigned int nr_relocs;
} hdr;
};
};

View File

@ -6,15 +6,14 @@
* also by log functions in the std plugin.
*/
enum __compel_log_levels
{
COMPEL_LOG_MSG, /* Print message regardless of log level */
COMPEL_LOG_ERROR, /* Errors only, when we're in trouble */
COMPEL_LOG_WARN, /* Warnings */
COMPEL_LOG_INFO, /* Informative, everything is fine */
COMPEL_LOG_DEBUG, /* Debug only */
enum __compel_log_levels {
COMPEL_LOG_MSG, /* Print message regardless of log level */
COMPEL_LOG_ERROR, /* Errors only, when we're in trouble */
COMPEL_LOG_WARN, /* Warnings */
COMPEL_LOG_INFO, /* Informative, everything is fine */
COMPEL_LOG_DEBUG, /* Debug only */
COMPEL_DEFAULT_LOGLEVEL = COMPEL_LOG_WARN
COMPEL_DEFAULT_LOGLEVEL = COMPEL_LOG_WARN
};
#endif /* UAPI_COMPEL_LOGLEVELS_H__ */

View File

@ -1,33 +1,31 @@
#ifndef UAPI_COMPEL_PLUGIN_H__
#define UAPI_COMPEL_PLUGIN_H__
#define __init __attribute__((__used__)) __attribute__ ((__section__(".compel.init")))
#define __exit __attribute__((__used__)) __attribute__ ((__section__(".compel.exit")))
#define __init __attribute__((__used__)) __attribute__((__section__(".compel.init")))
#define __exit __attribute__((__used__)) __attribute__((__section__(".compel.exit")))
#ifndef __ASSEMBLY__
typedef struct {
const char *name;
int (*init)(void);
void (*exit)(void);
const char *name;
int (*init)(void);
void (*exit)(void);
} plugin_init_t;
#define plugin_register(___desc) \
static const plugin_init_t * const \
___ptr__##___desc __init = &___desc;
#define plugin_register(___desc) static const plugin_init_t *const ___ptr__##___desc __init = &___desc;
#define PLUGIN_REGISTER(___id, ___name, ___init, ___exit) \
static const plugin_init_t __plugin_desc_##___id = { \
.name = ___name, \
.init = ___init, \
.exit = ___exit, \
}; \
#define PLUGIN_REGISTER(___id, ___name, ___init, ___exit) \
static const plugin_init_t __plugin_desc_##___id = { \
.name = ___name, \
.init = ___init, \
.exit = ___exit, \
}; \
plugin_register(__plugin_desc_##___id);
#define PLUGIN_REGISTER_DUMMY(___id) \
static const plugin_init_t __plugin_desc_##___id = { \
.name = #___id, \
}; \
#define PLUGIN_REGISTER_DUMMY(___id) \
static const plugin_init_t __plugin_desc_##___id = { \
.name = #___id, \
}; \
plugin_register(__plugin_desc_##___id);
#endif /* __ASSEMBLY__ */

View File

@ -19,40 +19,40 @@
*/
#ifndef PTRACE_SEIZE
# define PTRACE_SEIZE 0x4206
#define PTRACE_SEIZE 0x4206
#endif
#ifndef PTRACE_O_SUSPEND_SECCOMP
# define PTRACE_O_SUSPEND_SECCOMP (1 << 21)
#define PTRACE_O_SUSPEND_SECCOMP (1 << 21)
#endif
#ifndef PTRACE_INTERRUPT
# define PTRACE_INTERRUPT 0x4207
#define PTRACE_INTERRUPT 0x4207
#endif
#ifndef PTRACE_PEEKSIGINFO
#define PTRACE_PEEKSIGINFO 0x4209
#define PTRACE_PEEKSIGINFO 0x4209
/* Read signals from a shared (process wide) queue */
#define PTRACE_PEEKSIGINFO_SHARED (1 << 0)
#define PTRACE_PEEKSIGINFO_SHARED (1 << 0)
#endif
#ifndef PTRACE_GETREGSET
# define PTRACE_GETREGSET 0x4204
# define PTRACE_SETREGSET 0x4205
#define PTRACE_GETREGSET 0x4204
#define PTRACE_SETREGSET 0x4205
#endif
#ifndef PTRACE_GETSIGMASK
# define PTRACE_GETSIGMASK 0x420a
# define PTRACE_SETSIGMASK 0x420b
#define PTRACE_GETSIGMASK 0x420a
#define PTRACE_SETSIGMASK 0x420b
#endif
#ifndef PTRACE_SECCOMP_GET_FILTER
#define PTRACE_SECCOMP_GET_FILTER 0x420c
#define PTRACE_SECCOMP_GET_FILTER 0x420c
#endif
#ifndef PTRACE_SECCOMP_GET_METADATA
# define PTRACE_SECCOMP_GET_METADATA 0x420d
#define PTRACE_SECCOMP_GET_METADATA 0x420d
#endif /* PTRACE_SECCOMP_GET_METADATA */
/*
@ -61,17 +61,17 @@
* own identical definition for a while.
*/
typedef struct {
uint64_t filter_off; /* Input: which filter */
uint64_t flags; /* Output: filter's flags */
uint64_t filter_off; /* Input: which filter */
uint64_t flags; /* Output: filter's flags */
} seccomp_metadata_t;
#ifdef PTRACE_EVENT_STOP
# if PTRACE_EVENT_STOP == 7 /* Bad value from Linux 3.1-3.3, fixed in 3.4 */
# undef PTRACE_EVENT_STOP
# endif
#if PTRACE_EVENT_STOP == 7 /* Bad value from Linux 3.1-3.3, fixed in 3.4 */
#undef PTRACE_EVENT_STOP
#endif
#endif
#ifndef PTRACE_EVENT_STOP
# define PTRACE_EVENT_STOP 128
#define PTRACE_EVENT_STOP 128
#endif
extern int ptrace_suspend_seccomp(pid_t pid);

View File

@ -5,7 +5,7 @@
#define UAPI_COMPEL_SIGFRAME_COMMON_H__
#ifndef UAPI_COMPEL_ASM_SIGFRAME_H__
# error "Direct inclusion is forbidden, use <compel/asm/sigframe.h> instead"
#error "Direct inclusion is forbidden, use <compel/asm/sigframe.h> instead"
#endif
#include "common/compiler.h"
@ -15,49 +15,47 @@
struct rt_sigframe;
#ifndef SIGFRAME_MAX_OFFSET
# define SIGFRAME_MAX_OFFSET RT_SIGFRAME_OFFSET(0)
#define SIGFRAME_MAX_OFFSET RT_SIGFRAME_OFFSET(0)
#endif
#define RESTORE_STACK_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
#define RESTORE_STACK_ALIGN(x, a) (((x) + (a)-1) & ~((a)-1))
/* sigframe should be aligned on 64 byte for x86 and 8 bytes for arm */
#define RESTORE_STACK_SIGFRAME \
RESTORE_STACK_ALIGN(sizeof(struct rt_sigframe) + SIGFRAME_MAX_OFFSET, 64)
#define RESTORE_STACK_SIGFRAME RESTORE_STACK_ALIGN(sizeof(struct rt_sigframe) + SIGFRAME_MAX_OFFSET, 64)
#ifndef __ARCH_SI_PREAMBLE_SIZE
# define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
#endif
#define SI_MAX_SIZE 128
#define SI_MAX_SIZE 128
#ifndef SI_PAD_SIZE
# define SI_PAD_SIZE ((SI_MAX_SIZE - __ARCH_SI_PREAMBLE_SIZE) / sizeof(int))
#define SI_PAD_SIZE ((SI_MAX_SIZE - __ARCH_SI_PREAMBLE_SIZE) / sizeof(int))
#endif
typedef struct rt_siginfo {
int si_signo;
int si_errno;
int si_code;
int _pad[SI_PAD_SIZE];
int si_signo;
int si_errno;
int si_code;
int _pad[SI_PAD_SIZE];
} rt_siginfo_t;
typedef struct rt_sigaltstack {
void *ss_sp;
int ss_flags;
size_t ss_size;
void *ss_sp;
int ss_flags;
size_t ss_size;
} rt_stack_t;
struct rt_ucontext {
unsigned long uc_flags;
struct rt_ucontext *uc_link;
rt_stack_t uc_stack;
struct rt_sigcontext uc_mcontext;
k_rtsigset_t uc_sigmask; /* mask last for extensibility */
int _unused[32 - (sizeof (k_rtsigset_t) / sizeof (int))];
unsigned long uc_regspace[128] __attribute__((aligned(8)));
unsigned long uc_flags;
struct rt_ucontext *uc_link;
rt_stack_t uc_stack;
struct rt_sigcontext uc_mcontext;
k_rtsigset_t uc_sigmask; /* mask last for extensibility */
int _unused[32 - (sizeof(k_rtsigset_t) / sizeof(int))];
unsigned long uc_regspace[128] __attribute__((aligned(8)));
};
extern int __must_check sigreturn_prep_fpu_frame(struct rt_sigframe *frame,
struct rt_sigframe *rframe);
extern int __must_check sigreturn_prep_fpu_frame(struct rt_sigframe *frame, struct rt_sigframe *rframe);
#endif /* UAPI_COMPEL_SIGFRAME_COMMON_H__ */

View File

@ -5,15 +5,14 @@
* Task state, as returned by compel_wait_task()
* and used in arguments to compel_resume_task().
*/
enum __compel_task_state
{
COMPEL_TASK_ALIVE = 0x01,
COMPEL_TASK_DEAD = 0x02,
COMPEL_TASK_STOPPED = 0x03,
COMPEL_TASK_ZOMBIE = 0x06,
enum __compel_task_state {
COMPEL_TASK_ALIVE = 0x01,
COMPEL_TASK_DEAD = 0x02,
COMPEL_TASK_STOPPED = 0x03,
COMPEL_TASK_ZOMBIE = 0x06,
/* Don't ever change the above values, they are used by CRIU! */
COMPEL_TASK_MAX = 0x7f
COMPEL_TASK_MAX = 0x7f
};
#endif /* __COMPEL_UAPI_TASK_STATE_H__ */

View File

@ -6,7 +6,7 @@
extern int parasite_get_rpc_sock(void);
extern unsigned int __export_parasite_service_cmd;
extern void * __export_parasite_service_args_ptr;
extern void *__export_parasite_service_args_ptr;
extern int __must_check parasite_service(void);
/*

View File

@ -4,7 +4,7 @@
#include "compel/loglevels.h"
#include "common/compiler.h"
#define STD_LOG_SIMPLE_CHUNK 256
#define STD_LOG_SIMPLE_CHUNK 256
extern void std_log_set_fd(int fd);
extern void std_log_set_loglevel(enum __compel_log_levels level);
@ -23,8 +23,8 @@ extern int std_gettimeofday(struct timeval *tv, struct timezone *tz);
extern int std_vprint_num(char *buf, int blen, int num, char **ps);
extern void std_sprintf(char output[STD_LOG_SIMPLE_CHUNK], const char *format, ...)
__attribute__ ((__format__ (__printf__, 2, 3)));
__attribute__((__format__(__printf__, 2, 3)));
extern void print_on_level(unsigned int loglevel, const char *format, ...)
__attribute__ ((__format__ (__printf__, 2, 3)));
__attribute__((__format__(__printf__, 2, 3)));
#endif /* COMPEL_PLUGIN_STD_LOG_H__ */

View File

@ -6,20 +6,18 @@
#include <stdarg.h>
/* Standard file descriptors. */
#define STDIN_FILENO 0 /* Standard input. */
#define STDOUT_FILENO 1 /* Standard output. */
#define STDERR_FILENO 2 /* Standard error output. */
#define STDIN_FILENO 0 /* Standard input. */
#define STDOUT_FILENO 1 /* Standard output. */
#define STDERR_FILENO 2 /* Standard error output. */
extern void std_dputc(int fd, char c);
extern void std_dputs(int fd, const char *s);
extern void std_vdprintf(int fd, const char *format, va_list args);
extern void std_dprintf(int fd, const char *format, ...)
__attribute__ ((__format__ (__printf__, 2, 3)));
extern void std_dprintf(int fd, const char *format, ...) __attribute__((__format__(__printf__, 2, 3)));
#define std_printf(fmt, ...) std_dprintf(STDOUT_FILENO, fmt, ##__VA_ARGS__)
#define std_puts(s) std_dputs(STDOUT_FILENO, s)
#define std_putchar(c) std_dputc(STDOUT_FILENO, c)
#define std_printf(fmt, ...) std_dprintf(STDOUT_FILENO, fmt, ##__VA_ARGS__)
#define std_puts(s) std_dputs(STDOUT_FILENO, s)
#define std_putchar(c) std_dputc(STDOUT_FILENO, c)
extern unsigned long std_strtoul(const char *nptr, char **endptr, int base);
extern int std_strcmp(const char *cs, const char *ct);

View File

@ -44,7 +44,7 @@ struct clone_args;
typedef unsigned long aio_context_t;
#ifndef F_GETFD
# define F_GETFD 1
#define F_GETFD 1
#endif
struct krlimit {
@ -57,7 +57,6 @@ typedef int kernel_timer_t;
#include <compel/plugins/std/asm/syscall-types.h>
extern long sys_preadv_raw(int fd, struct iovec *iov, unsigned long nr, unsigned long pos_l, unsigned long pos_h);
static inline long sys_preadv(int fd, struct iovec *iov, unsigned long nr, off_t off)
@ -67,7 +66,7 @@ static inline long sys_preadv(int fd, struct iovec *iov, unsigned long nr, off_t
#elif BITS_PER_LONG == 32
return sys_preadv_raw(fd, iov, nr, off, ((uint64_t)off) >> 32);
#else
# error "BITS_PER_LONG isn't defined"
#error "BITS_PER_LONG isn't defined"
#endif
}

View File

@ -5,7 +5,6 @@ extern int save_task_regs(void *, user_regs_struct_t *, user_fpregs_struct_t *);
extern int arch_alloc_thread_info(CoreEntry *core);
extern void arch_free_thread_info(CoreEntry *core);
static inline void core_put_tls(CoreEntry *core, tls_t tls)
{
core->ti_aarch64->tls = tls;

View File

@ -1,7 +1,7 @@
#ifndef __CR_ASM_KERNDAT_H__
#define __CR_ASM_KERNDAT_H__
#define kdat_compatible_cr() 0
#define kdat_can_map_vdso() 0
#define kdat_compatible_cr() 0
#define kdat_can_map_vdso() 0
#endif /* __CR_ASM_KERNDAT_H__ */

View File

@ -4,7 +4,7 @@
static inline void arch_get_tls(tls_t *ptls)
{
tls_t tls;
asm("mrs %0, tpidr_el0" : "=r" (tls));
asm("mrs %0, tpidr_el0" : "=r"(tls));
*ptls = tls;
}

View File

@ -5,6 +5,7 @@
#include "images/core.pb-c.h"
/* clang-format off */
#define JUMP_TO_RESTORER_BLOB(new_sp, restore_task_exec_start, \
task_args) \
asm volatile( \
@ -16,13 +17,13 @@
"r"(restore_task_exec_start), \
"r"(task_args) \
: "x0", "memory")
/* clang-format on */
static inline void core_get_tls(CoreEntry *pcore, tls_t *ptls)
{
*ptls = pcore->ti_aarch64->tls;
}
int restore_fpu(struct rt_sigframe *sigframe, CoreEntry *core);
#endif

View File

@ -9,6 +9,7 @@
#include <compel/asm/sigframe.h>
/* clang-format off */
#define RUN_CLONE_RESTORE_FN(ret, clone_flags, new_sp, parent_tid, \
thread_args, clone_restore_fn) \
asm volatile( \
@ -112,20 +113,25 @@
: \
: "r"(ret) \
: "sp", "x0", "memory")
/* clang-format on */
#define arch_map_vdso(map, compat) -1
#define arch_map_vdso(map, compat) -1
int restore_gpregs(struct rt_sigframe *f, UserAarch64RegsEntry *r);
int restore_nonsigframe_gpregs(UserAarch64RegsEntry *r);
static inline void restore_tls(tls_t *ptls)
{
asm("msr tpidr_el0, %0" : : "r" (*ptls));
asm("msr tpidr_el0, %0" : : "r"(*ptls));
}
static inline void *alloc_compat_syscall_stack(void) { return NULL; }
static inline void free_compat_syscall_stack(void *stack32) { }
static inline void *alloc_compat_syscall_stack(void)
{
return NULL;
}
static inline void free_compat_syscall_stack(void *stack32)
{
}
static inline int arch_compat_rt_sigaction(void *stack, int sig, void *act)
{
return -1;

View File

@ -12,7 +12,7 @@
#include <compel/plugins/std/asm/syscall-types.h>
#define core_is_compat(core) false
#define core_is_compat(core) false
typedef UserAarch64RegsEntry UserRegsEntry;
@ -22,8 +22,14 @@ typedef UserAarch64RegsEntry UserRegsEntry;
#define TI_SP(core) ((core)->ti_aarch64->gpregs->sp)
static inline void *decode_pointer(uint64_t v) { return (void*)v; }
static inline uint64_t encode_pointer(void *p) { return (uint64_t)p; }
static inline void *decode_pointer(uint64_t v)
{
return (void *)v;
}
static inline uint64_t encode_pointer(void *p)
{
return (uint64_t)p;
}
#define AT_VECTOR_SIZE 40
typedef uint64_t auxv_t;

View File

@ -9,24 +9,20 @@
* This is a minimal amount of symbols
* we should support at the moment.
*/
#define VDSO_SYMBOL_MAX 4
#define VDSO_SYMBOL_GTOD 2
#define VDSO_SYMBOL_MAX 4
#define VDSO_SYMBOL_GTOD 2
/*
* Workaround for VDSO array symbol table's relocation.
* XXX: remove when compel/piegen will support aarch64.
*/
#define ARCH_VDSO_SYMBOLS_LIST \
const char* aarch_vdso_symbol1 = "__kernel_clock_getres"; \
const char* aarch_vdso_symbol2 = "__kernel_clock_gettime"; \
const char* aarch_vdso_symbol3 = "__kernel_gettimeofday"; \
const char* aarch_vdso_symbol4 = "__kernel_rt_sigreturn";
#define ARCH_VDSO_SYMBOLS_LIST \
const char *aarch_vdso_symbol1 = "__kernel_clock_getres"; \
const char *aarch_vdso_symbol2 = "__kernel_clock_gettime"; \
const char *aarch_vdso_symbol3 = "__kernel_gettimeofday"; \
const char *aarch_vdso_symbol4 = "__kernel_rt_sigreturn";
#define ARCH_VDSO_SYMBOLS \
aarch_vdso_symbol1, \
aarch_vdso_symbol2, \
aarch_vdso_symbol3, \
aarch_vdso_symbol4
#define ARCH_VDSO_SYMBOLS aarch_vdso_symbol1, aarch_vdso_symbol2, aarch_vdso_symbol3, aarch_vdso_symbol4
extern void write_intraprocedure_branch(unsigned long to, unsigned long from);

View File

@ -5,7 +5,6 @@ extern int save_task_regs(void *, user_regs_struct_t *, user_fpregs_struct_t *);
extern int arch_alloc_thread_info(CoreEntry *core);
extern void arch_free_thread_info(CoreEntry *core);
static inline void core_put_tls(CoreEntry *core, tls_t tls)
{
core->ti_arm->tls = tls;

View File

@ -1,7 +1,7 @@
#ifndef __CR_ASM_KERNDAT_H__
#define __CR_ASM_KERNDAT_H__
#define kdat_compatible_cr() 0
#define kdat_can_map_vdso() 0
#define kdat_compatible_cr() 0
#define kdat_can_map_vdso() 0
#endif /* __CR_ASM_KERNDAT_H__ */

View File

@ -4,7 +4,7 @@
/* kuser_get_tls() kernel-provided user-helper, the address is emulated */
static inline void arch_get_tls(tls_t *ptls)
{
*ptls = ((tls_t (*)(void))0xffff0fe0)();
*ptls = ((tls_t(*)(void))0xffff0fe0)();
}
#endif

View File

@ -5,6 +5,7 @@
#include "images/core.pb-c.h"
/* clang-format off */
#define JUMP_TO_RESTORER_BLOB(new_sp, restore_task_exec_start, \
task_args) \
asm volatile( \
@ -17,13 +18,13 @@
"r"(restore_task_exec_start), \
"r"(task_args) \
: "r0", "r1", "memory")
/* clang-format on */
static inline void core_get_tls(CoreEntry *pcore, tls_t *ptls)
{
*ptls = pcore->ti_arm->tls;
}
int restore_fpu(struct rt_sigframe *sigframe, CoreEntry *core);
#endif

View File

@ -6,6 +6,7 @@
#include <compel/asm/sigframe.h>
/* clang-format off */
#define RUN_CLONE_RESTORE_FN(ret, clone_flags, new_sp, parent_tid, \
thread_args, clone_restore_fn) \
asm volatile( \
@ -108,32 +109,35 @@
: \
: "r"(ret) \
: "memory")
/* clang-format on */
#define arch_map_vdso(map, compat) -1
#define arch_map_vdso(map, compat) -1
int restore_gpregs(struct rt_sigframe *f, UserArmRegsEntry *r);
int restore_nonsigframe_gpregs(UserArmRegsEntry *r);
#define ARCH_HAS_SHMAT_HOOK
unsigned long arch_shmat(int shmid, void *shmaddr,
int shmflg, unsigned long size);
unsigned long arch_shmat(int shmid, void *shmaddr, int shmflg, unsigned long size);
static inline void restore_tls(tls_t *ptls) {
asm (
"mov r7, #15 \n"
"lsl r7, #16 \n"
"mov r0, #5 \n"
"add r7, r0 \n" /* r7 = 0xF005 */
"ldr r0, [%0] \n"
"svc #0 \n"
:
: "r"(ptls)
: "r0", "r7"
);
static inline void restore_tls(tls_t *ptls)
{
asm("mov r7, #15 \n"
"lsl r7, #16 \n"
"mov r0, #5 \n"
"add r7, r0 \n" /* r7 = 0xF005 */
"ldr r0, [%0] \n"
"svc #0 \n"
:
: "r"(ptls)
: "r0", "r7");
}
static inline void *alloc_compat_syscall_stack(void) { return NULL; }
static inline void free_compat_syscall_stack(void *stack32) { }
static inline void *alloc_compat_syscall_stack(void)
{
return NULL;
}
static inline void free_compat_syscall_stack(void *stack32)
{
}
static inline int arch_compat_rt_sigaction(void *stack, int sig, void *act)
{
return -1;

View File

@ -11,7 +11,7 @@
#include <compel/plugins/std/asm/syscall-types.h>
#define core_is_compat(core) false
#define core_is_compat(core) false
typedef UserArmRegsEntry UserRegsEntry;
@ -21,10 +21,16 @@ typedef UserArmRegsEntry UserRegsEntry;
#define TI_SP(core) ((core)->ti_arm->gpregs->sp)
static inline void *decode_pointer(u64 v) { return (void*)(u32)v; }
static inline u64 encode_pointer(void *p) { return (u32)p; }
static inline void *decode_pointer(u64 v)
{
return (void *)(u32)v;
}
static inline u64 encode_pointer(void *p)
{
return (u32)p;
}
#define AT_VECTOR_SIZE 40
#define AT_VECTOR_SIZE 40
typedef uint32_t auxv_t;
typedef uint32_t tls_t;

View File

@ -9,13 +9,11 @@
*
* Poke from kernel file arch/arm/vdso/vdso.lds.S
*/
#define VDSO_SYMBOL_MAX 2
#define VDSO_SYMBOL_GTOD 1
#define ARCH_VDSO_SYMBOLS_LIST \
const char* aarch_vdso_symbol1 = "__vdso_clock_gettime"; \
const char* aarch_vdso_symbol2 = "__vdso_gettimeofday";
#define ARCH_VDSO_SYMBOLS \
aarch_vdso_symbol1, \
aarch_vdso_symbol2,
#define VDSO_SYMBOL_MAX 2
#define VDSO_SYMBOL_GTOD 1
#define ARCH_VDSO_SYMBOLS_LIST \
const char *aarch_vdso_symbol1 = "__vdso_clock_gettime"; \
const char *aarch_vdso_symbol2 = "__vdso_gettimeofday";
#define ARCH_VDSO_SYMBOLS aarch_vdso_symbol1, aarch_vdso_symbol2,
#endif /* __CR_ASM_VDSO_H__ */

View File

@ -1,7 +1,7 @@
#ifndef __CR_ASM_KERNDAT_H__
#define __CR_ASM_KERNDAT_H__
#define kdat_compatible_cr() 0
#define kdat_can_map_vdso() 0
#define kdat_compatible_cr() 0
#define kdat_can_map_vdso() 0
#endif /* __CR_ASM_KERNDAT_H__ */

View File

@ -4,6 +4,7 @@
#include "asm/restorer.h"
#include "images/core.pb-c.h"
/* clang-format off */
#define JUMP_TO_RESTORER_BLOB(new_sp, restore_task_exec_start, task_args) \
asm volatile( \
"move $4, %0 \n" \
@ -16,13 +17,13 @@
:"r"(task_args),"r"(restore_task_exec_start), \
"g"(new_sp) \
: "$25", "$4","$5")
/* clang-format on */
static inline void core_get_tls(CoreEntry *pcore, tls_t *ptls)
{
*ptls = pcore->ti_mips->tls;
}
int restore_fpu(struct rt_sigframe *sigframe, CoreEntry *core);
#endif

View File

@ -7,14 +7,16 @@
#include <compel/plugins/std/syscall-codes.h>
#include <compel/asm/sigframe.h>
static inline void restore_tls(tls_t *ptls) {
asm volatile(
"move $4, %0 \n"
"li $2, "__stringify(__NR_set_thread_area)" \n"
"syscall \n"
static inline void restore_tls(tls_t *ptls)
{
/* clang-format off */
asm volatile("move $4, %0 \n"
"li $2, " __stringify(__NR_set_thread_area) " \n"
"syscall \n"
:
: "r"(*ptls)
: "$4","$2","memory");
: "$4", "$2", "memory");
/* clang-format on */
}
static inline int arch_compat_rt_sigaction(void *stack, int sig, void *act)
{
@ -25,6 +27,7 @@ static inline int set_compat_robust_list(uint32_t head_ptr, uint32_t len)
return -1;
}
/* clang-format off */
#define RUN_CLONE_RESTORE_FN(ret, clone_flags, new_sp, parent_tid, \
thread_args, clone_restore_fn) \
asm volatile( \
@ -67,17 +70,22 @@ static inline int set_compat_robust_list(uint32_t head_ptr, uint32_t len)
pr_err("This architecture does not support clone3() with set_tid, yet!\n"); \
ret = -1; \
} while (0)
/* clang-format on */
#define kdat_compatible_cr() 0
#define arch_map_vdso(map, compat) -1
#define kdat_compatible_cr() 0
#define arch_map_vdso(map, compat) -1
static inline void *alloc_compat_syscall_stack(void) { return NULL; }
static inline void free_compat_syscall_stack(void *stack32) { }
static inline void *alloc_compat_syscall_stack(void)
{
return NULL;
}
static inline void free_compat_syscall_stack(void *stack32)
{
}
int restore_gpregs(struct rt_sigframe *f, UserMipsRegsEntry *r);
int restore_nonsigframe_gpregs(UserMipsRegsEntry *r);
#define ARCH_HAS_SHMAT_HOOK
unsigned long arch_shmat(int shmid, void *shmaddr,
int shmflg, unsigned long size);
unsigned long arch_shmat(int shmid, void *shmaddr, int shmflg, unsigned long size);
#endif

View File

@ -12,7 +12,7 @@
#include "images/core.pb-c.h"
#define core_is_compat(core) false
#define core_is_compat(core) false
#define CORE_ENTRY__MARCH CORE_ENTRY__MARCH__MIPS
@ -20,11 +20,16 @@
typedef UserMipsRegsEntry UserRegsEntry;
static inline u64 encode_pointer(void *p) { return (u64)p; }
static inline void *decode_pointer(u64 v) { return (void*)v; }
static inline u64 encode_pointer(void *p)
{
return (u64)p;
}
static inline void *decode_pointer(u64 v)
{
return (void *)v;
}
#define AT_VECTOR_SIZE 44
#define AT_VECTOR_SIZE 44
typedef uint64_t auxv_t;
typedef unsigned long tls_t;

View File

@ -12,16 +12,12 @@
* This is a minimal amount of symbols
* we should support at the moment.
*/
#define VDSO_SYMBOL_MAX 3
#define VDSO_SYMBOL_GTOD 0
#define ARCH_VDSO_SYMBOLS_LIST \
const char* aarch_vdso_symbol1 = "__vdso_clock_gettime"; \
const char* aarch_vdso_symbol2 = "__vdso_gettimeofday"; \
const char* aarch_vdso_symbol3 = "__vdso_clock_getres";
#define ARCH_VDSO_SYMBOLS \
aarch_vdso_symbol1, \
aarch_vdso_symbol2, \
aarch_vdso_symbol3,
#define VDSO_SYMBOL_MAX 3
#define VDSO_SYMBOL_GTOD 0
#define ARCH_VDSO_SYMBOLS_LIST \
const char *aarch_vdso_symbol1 = "__vdso_clock_gettime"; \
const char *aarch_vdso_symbol2 = "__vdso_gettimeofday"; \
const char *aarch_vdso_symbol3 = "__vdso_clock_getres";
#define ARCH_VDSO_SYMBOLS aarch_vdso_symbol1, aarch_vdso_symbol2, aarch_vdso_symbol3,
#endif /* __CR_ASM_VDSO_H__ */

View File

@ -5,7 +5,6 @@ extern int save_task_regs(void *, user_regs_struct_t *, user_fpregs_struct_t *);
extern int arch_alloc_thread_info(CoreEntry *core);
extern void arch_free_thread_info(CoreEntry *core);
#define core_put_tls(core, tls)
#define get_task_futex_robust_list_compat(pid, info) -1

View File

@ -1,7 +1,7 @@
#ifndef __CR_ASM_KERNDAT_H__
#define __CR_ASM_KERNDAT_H__
#define kdat_compatible_cr() 0
#define kdat_can_map_vdso() 0
#define kdat_compatible_cr() 0
#define kdat_can_map_vdso() 0
#endif /* __CR_ASM_KERNDAT_H__ */

View File

@ -2,6 +2,9 @@
#define __ASM_PARASITE_H__
/* TLS is accessed through r13, which is already processed */
static inline void arch_get_tls(tls_t *ptls) { (void)ptls; }
static inline void arch_get_tls(tls_t *ptls)
{
(void)ptls;
}
#endif

View File

@ -9,6 +9,7 @@
* Set R2 to blob + 8000 which is the default value
* Jump to restore_task_exec_start + 8 since R2 is already set (local call)
*/
/* clang-format off */
#define JUMP_TO_RESTORER_BLOB(new_sp, restore_task_exec_start, \
task_args) \
asm volatile( \
@ -22,6 +23,7 @@
"r"((unsigned long)restore_task_exec_start), \
"r"(task_args) \
: "3", "12")
/* clang-format on */
/* There is nothing to do since TLS is accessed through r13 */
#define core_get_tls(pcore, ptls)

View File

@ -14,9 +14,10 @@
*
* See glibc sysdeps/powerpc/powerpc64/sysdep.h for FRAME_MIN_SIZE defines
*/
#define RUN_CLONE_RESTORE_FN(ret, clone_flags, new_sp, parent_tid, \
/* clang-format off */
#define RUN_CLONE_RESTORE_FN(ret, clone_flags, new_sp, parent_tid, \
thread_args, clone_restore_fn) \
asm volatile( \
asm volatile( \
"clone_emul: \n" \
"/* Save fn, args, stack across syscall. */ \n" \
"mr 14, %5 /* clone_restore_fn in r14 */ \n" \
@ -88,22 +89,31 @@
"r"(clone_restore_fn), /* %3 */ \
"r"(args) /* %4 */ \
: "memory","0","3","4","5","14","15")
/* clang-format on */
#define arch_map_vdso(map, compat) -1
#define arch_map_vdso(map, compat) -1
int restore_gpregs(struct rt_sigframe *f, UserPpc64RegsEntry *r);
int restore_nonsigframe_gpregs(UserPpc64RegsEntry *r);
/* Nothing to do, TLS is accessed through r13 */
static inline void restore_tls(tls_t *ptls) { (void)ptls; }
static inline void restore_tls(tls_t *ptls)
{
(void)ptls;
}
/*
* Defined in arch/ppc64/syscall-common-ppc64.S
*/
unsigned long sys_shmat(int shmid, const void *shmaddr, int shmflg);
static inline void *alloc_compat_syscall_stack(void) { return NULL; }
static inline void free_compat_syscall_stack(void *stack32) { }
static inline void *alloc_compat_syscall_stack(void)
{
return NULL;
}
static inline void free_compat_syscall_stack(void *stack32)
{
}
static inline int arch_compat_rt_sigaction(void *stack, int sig, void *act)
{
return -1;

View File

@ -13,14 +13,20 @@
typedef UserPpc64RegsEntry UserRegsEntry;
#define CORE_ENTRY__MARCH CORE_ENTRY__MARCH__PPC64
#define CORE_ENTRY__MARCH CORE_ENTRY__MARCH__PPC64
#define core_is_compat(core) false
#define core_is_compat(core) false
#define CORE_THREAD_ARCH_INFO(core) core->ti_ppc64
static inline void *decode_pointer(uint64_t v) { return (void*)v; }
static inline uint64_t encode_pointer(void *p) { return (uint64_t)p; }
static inline void *decode_pointer(uint64_t v)
{
return (void *)v;
}
static inline uint64_t encode_pointer(void *p)
{
return (uint64_t)p;
}
/*
* Copied from the following kernel header files :
@ -28,11 +34,11 @@ static inline uint64_t encode_pointer(void *p) { return (uint64_t)p; }
* arch/powerpc/include/uapi/asm/auxvec.h
* include/linux/mm_types.h
*/
#define AT_VECTOR_SIZE_BASE 20
#define AT_VECTOR_SIZE_BASE 20
#if !defined AT_VECTOR_SIZE_ARCH
#define AT_VECTOR_SIZE_ARCH 6
#define AT_VECTOR_SIZE_ARCH 6
#endif
#define AT_VECTOR_SIZE (2*(AT_VECTOR_SIZE_ARCH + AT_VECTOR_SIZE_BASE + 1))
#define AT_VECTOR_SIZE (2 * (AT_VECTOR_SIZE_ARCH + AT_VECTOR_SIZE_BASE + 1))
typedef uint64_t auxv_t;

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@ -12,30 +12,22 @@
* Note that '__kernel_datapage_offset' is not a service but mostly a data
* inside the text page which should not be used as is from user space.
*/
#define VDSO_SYMBOL_MAX 10
#define VDSO_SYMBOL_GTOD 5
#define ARCH_VDSO_SYMBOLS_LIST \
const char* aarch_vdso_symbol1 = "__kernel_clock_getres"; \
const char* aarch_vdso_symbol2 = "__kernel_clock_gettime"; \
const char* aarch_vdso_symbol3 = "__kernel_get_syscall_map"; \
const char* aarch_vdso_symbol4 = "__kernel_get_tbfreq"; \
const char* aarch_vdso_symbol5 = "__kernel_getcpu"; \
const char* aarch_vdso_symbol6 = "__kernel_gettimeofday"; \
const char* aarch_vdso_symbol7 = "__kernel_sigtramp_rt64"; \
const char* aarch_vdso_symbol8 = "__kernel_sync_dicache"; \
const char* aarch_vdso_symbol9 = "__kernel_sync_dicache_p5"; \
const char* aarch_vdso_symbol10 = "__kernel_time";
#define VDSO_SYMBOL_MAX 10
#define VDSO_SYMBOL_GTOD 5
#define ARCH_VDSO_SYMBOLS_LIST \
const char *aarch_vdso_symbol1 = "__kernel_clock_getres"; \
const char *aarch_vdso_symbol2 = "__kernel_clock_gettime"; \
const char *aarch_vdso_symbol3 = "__kernel_get_syscall_map"; \
const char *aarch_vdso_symbol4 = "__kernel_get_tbfreq"; \
const char *aarch_vdso_symbol5 = "__kernel_getcpu"; \
const char *aarch_vdso_symbol6 = "__kernel_gettimeofday"; \
const char *aarch_vdso_symbol7 = "__kernel_sigtramp_rt64"; \
const char *aarch_vdso_symbol8 = "__kernel_sync_dicache"; \
const char *aarch_vdso_symbol9 = "__kernel_sync_dicache_p5"; \
const char *aarch_vdso_symbol10 = "__kernel_time";
#define ARCH_VDSO_SYMBOLS \
aarch_vdso_symbol1, \
aarch_vdso_symbol2, \
aarch_vdso_symbol3, \
aarch_vdso_symbol4, \
aarch_vdso_symbol5, \
aarch_vdso_symbol6, \
aarch_vdso_symbol7, \
aarch_vdso_symbol8, \
aarch_vdso_symbol9, \
aarch_vdso_symbol10
#define ARCH_VDSO_SYMBOLS \
aarch_vdso_symbol1, aarch_vdso_symbol2, aarch_vdso_symbol3, aarch_vdso_symbol4, aarch_vdso_symbol5, \
aarch_vdso_symbol6, aarch_vdso_symbol7, aarch_vdso_symbol8, aarch_vdso_symbol9, aarch_vdso_symbol10
#endif /* __CR_ASM_VDSO_H__ */

View File

@ -5,7 +5,9 @@ int save_task_regs(void *arg, user_regs_struct_t *u, user_fpregs_struct_t *f);
int arch_alloc_thread_info(CoreEntry *core);
void arch_free_thread_info(CoreEntry *core);
static inline void core_put_tls(CoreEntry *core, tls_t tls) { }
static inline void core_put_tls(CoreEntry *core, tls_t tls)
{
}
#define get_task_futex_robust_list_compat(pid, info) -1

View File

@ -1,7 +1,7 @@
#ifndef __CR_ASM_KERNDAT_H__
#define __CR_ASM_KERNDAT_H__
#define kdat_compatible_cr() 0
#define kdat_can_map_vdso() 0
#define kdat_compatible_cr() 0
#define kdat_can_map_vdso() 0
#endif /* __CR_ASM_KERNDAT_H__ */

View File

@ -2,6 +2,9 @@
#define __ASM_PARASITE_H__
/* TLS is accessed through %a01, which is already processed */
static inline void arch_get_tls(tls_t *ptls) { (void)ptls; }
static inline void arch_get_tls(tls_t *ptls)
{
(void)ptls;
}
#endif

View File

@ -7,6 +7,7 @@
/*
* Load stack to %r15, return address in %r14 and argument 1 into %r2
*/
/* clang-format off */
#define JUMP_TO_RESTORER_BLOB(new_sp, restore_task_exec_start, \
task_args) \
asm volatile( \
@ -19,6 +20,7 @@
"d"((unsigned long)restore_task_exec_start), \
"d" (task_args) \
: "2", "14", "memory")
/* clang-format on */
/* There is nothing to do since TLS is accessed through %a01 */
#define core_get_tls(pcore, ptls)

View File

@ -11,6 +11,7 @@
/*
* Clone trampoline - see glibc sysdeps/unix/sysv/linux/s390/s390-64/clone.S
*/
/* clang-format off */
#define RUN_CLONE_RESTORE_FN(ret, clone_flags, new_sp, parent_tid, \
thread_args, clone_restore_fn) \
asm volatile( \
@ -75,20 +76,28 @@
"d"(clone_restore_fn), \
"d"(args) \
: "0", "1", "2", "3", "4", "5", "cc", "memory")
/* clang-format on */
#define arch_map_vdso(map, compat) -1
#define arch_map_vdso(map, compat) -1
int restore_gpregs(struct rt_sigframe *f, UserS390RegsEntry *r);
int restore_nonsigframe_gpregs(UserS390RegsEntry *r);
unsigned long sys_shmat(int shmid, const void *shmaddr, int shmflg);
unsigned long sys_mmap(void *addr, unsigned long len, unsigned long prot,
unsigned long flags, unsigned long fd,
unsigned long sys_mmap(void *addr, unsigned long len, unsigned long prot, unsigned long flags, unsigned long fd,
unsigned long offset);
static inline void restore_tls(tls_t *ptls) { (void)ptls; }
static inline void *alloc_compat_syscall_stack(void) { return NULL; }
static inline void free_compat_syscall_stack(void *stack32) { }
static inline void restore_tls(tls_t *ptls)
{
(void)ptls;
}
static inline void *alloc_compat_syscall_stack(void)
{
return NULL;
}
static inline void free_compat_syscall_stack(void *stack32)
{
}
static inline int arch_compat_rt_sigaction(void *stack, int sig, void *act)
{
return -1;

View File

@ -15,21 +15,27 @@ typedef UserS390RegsEntry UserRegsEntry;
#define CORE_ENTRY__MARCH CORE_ENTRY__MARCH__S390
#define core_is_compat(core) false
#define core_is_compat(core) false
#define CORE_THREAD_ARCH_INFO(core) core->ti_s390
static inline u64 encode_pointer(void *p) { return (u64) p; }
static inline void *decode_pointer(u64 v) { return (void *) v; }
static inline u64 encode_pointer(void *p)
{
return (u64)p;
}
static inline void *decode_pointer(u64 v)
{
return (void *)v;
}
/*
* See also:
* * arch/s390/include/uapi/asm/auxvec.h
* * include/linux/auxvec.h
*/
#define AT_VECTOR_SIZE_BASE 20
#define AT_VECTOR_SIZE_ARCH 1
#define AT_VECTOR_SIZE (2*(AT_VECTOR_SIZE_ARCH + AT_VECTOR_SIZE_BASE + 1))
#define AT_VECTOR_SIZE_BASE 20
#define AT_VECTOR_SIZE_ARCH 1
#define AT_VECTOR_SIZE (2 * (AT_VECTOR_SIZE_ARCH + AT_VECTOR_SIZE_BASE + 1))
typedef uint64_t auxv_t;
typedef uint64_t tls_t;

View File

@ -8,22 +8,18 @@
* This is a minimal amount of symbols
* we should support at the moment.
*/
#define VDSO_SYMBOL_MAX 4
#define VDSO_SYMBOL_GTOD 0
#define VDSO_SYMBOL_MAX 4
#define VDSO_SYMBOL_GTOD 0
/*
* These definitions are used in pie/util-vdso.c to initialize the vdso symbol
* name string table 'vdso_symbols'
*/
#define ARCH_VDSO_SYMBOLS_LIST \
const char* aarch_vdso_symbol1 = "__kernel_gettimeofday"; \
const char* aarch_vdso_symbol2 = "__kernel_clock_gettime"; \
const char* aarch_vdso_symbol3 = "__kernel_clock_getres"; \
const char* aarch_vdso_symbol4 = "__kernel_getcpu";
#define ARCH_VDSO_SYMBOLS \
aarch_vdso_symbol1, \
aarch_vdso_symbol2, \
aarch_vdso_symbol3, \
aarch_vdso_symbol4
#define ARCH_VDSO_SYMBOLS_LIST \
const char *aarch_vdso_symbol1 = "__kernel_gettimeofday"; \
const char *aarch_vdso_symbol2 = "__kernel_clock_gettime"; \
const char *aarch_vdso_symbol3 = "__kernel_clock_getres"; \
const char *aarch_vdso_symbol4 = "__kernel_getcpu";
#define ARCH_VDSO_SYMBOLS aarch_vdso_symbol1, aarch_vdso_symbol2, aarch_vdso_symbol3, aarch_vdso_symbol4
#endif /* __CR_ASM_VDSO_H__ */

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