From ec6dc2d5c0de5b1459ba0b6a91b686ca1db2fdf9 Mon Sep 17 00:00:00 2001
From: znley <shanjiantao@loongson.cn>
Date: Mon, 12 Jun 2023 15:09:22 +0800
Subject: [PATCH] images: add loongarch64 core image

Signed-off-by: znley <shanjiantao@loongson.cn>
---
 images/Makefile               |  1 +
 images/core-loongarch64.proto | 23 +++++++++++++++++++++++
 images/core.proto             |  3 +++
 3 files changed, 27 insertions(+)
 create mode 100755 images/core-loongarch64.proto

diff --git a/images/Makefile b/images/Makefile
index 004e22ec3..ca85b1a21 100644
--- a/images/Makefile
+++ b/images/Makefile
@@ -2,6 +2,7 @@ proto-obj-y	+= stats.o
 proto-obj-y	+= core.o
 proto-obj-y	+= core-x86.o
 proto-obj-y	+= core-mips.o
+proto-obj-y	+= core-loongarch64.o
 proto-obj-y	+= core-arm.o
 proto-obj-y	+= core-aarch64.o
 proto-obj-y	+= core-ppc64.o
diff --git a/images/core-loongarch64.proto b/images/core-loongarch64.proto
new file mode 100755
index 000000000..8258f006e
--- /dev/null
+++ b/images/core-loongarch64.proto
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: MIT
+
+syntax = "proto2";
+
+import "opts.proto";
+
+message user_loongarch64_gpregs_entry {
+	repeated uint64 regs	= 1;
+	required uint64 pc		= 2;
+}
+
+message user_loongarch64_fpregs_entry {
+	repeated uint64 regs    = 1;
+	required uint64 fcc     = 2;
+	required uint32 fcsr    = 3;
+}
+
+message thread_info_loongarch64 {
+	required uint64	clear_tid_addr	= 1[(criu).hex = true];
+	required uint64	tls				= 2;
+	required user_loongarch64_gpregs_entry	gpregs	= 3[(criu).hex = true];
+	required user_loongarch64_fpregs_entry	fpregs	= 4[(criu).hex = true];
+}
diff --git a/images/core.proto b/images/core.proto
index eddd1dc55..1882fe8e4 100644
--- a/images/core.proto
+++ b/images/core.proto
@@ -8,6 +8,7 @@ import "core-aarch64.proto";
 import "core-ppc64.proto";
 import "core-s390.proto";
 import "core-mips.proto";
+import "core-loongarch64.proto";
 
 import "rlimit.proto";
 import "timer.proto";
@@ -122,6 +123,7 @@ message core_entry {
 		PPC64		= 4;
 		S390		= 5;
 		MIPS		= 6;
+		LOONGARCH64		= 7;
 	}
 
 	required march			mtype		= 1;
@@ -131,6 +133,7 @@ message core_entry {
 	optional thread_info_ppc64	ti_ppc64	= 9;
 	optional thread_info_s390	ti_s390		= 10;
 	optional thread_info_mips	ti_mips		= 11;
+	optional thread_info_loongarch64	ti_loongarch64  = 12;
 
 	optional task_core_entry	tc		= 3;
 	optional task_kobj_ids_entry	ids		= 4;