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https://github.com/checkpoint-restore/criu
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4485723f80
Since in criu we can't choose proper arch inside include statements (well, it will simply require more ifdefs), I generate include/common/asm symlink to point proper architecture. travis-ci: success for Common headers Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Signed-off-by: Pavel Emelyanov <xemul@virtuozzo.com>
132 lines
2.5 KiB
C
132 lines
2.5 KiB
C
#ifndef __CR_ATOMIC_H__
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#define __CR_ATOMIC_H__
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#include "common/arch/arm/asm/processor.h"
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typedef struct {
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int counter;
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} atomic_t;
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/* Copied from the Linux kernel header arch/arm/include/asm/atomic.h */
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#if defined(CONFIG_ARMV7)
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#define smp_mb() __asm__ __volatile__ ("dmb" : : : "memory")
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static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
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{
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int oldval;
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unsigned long res;
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smp_mb();
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prefetchw(&ptr->counter);
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do {
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__asm__ __volatile__("@ atomic_cmpxchg\n"
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"ldrex %1, [%3]\n"
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"mov %0, #0\n"
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"teq %1, %4\n"
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"strexeq %0, %5, [%3]\n"
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: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
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: "r" (&ptr->counter), "Ir" (old), "r" (new)
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: "cc");
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} while (res);
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smp_mb();
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return oldval;
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}
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#elif defined(CONFIG_ARMV6)
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/* SMP isn't supported for ARMv6 */
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#define smp_mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory")
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static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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int ret;
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ret = v->counter;
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if (ret == old)
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v->counter = new;
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return ret;
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}
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#else
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#error ARM architecture version (CONFIG_ARMV*) not set or unsupported.
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#endif
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static inline int atomic_read(const atomic_t *v)
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{
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return (*(volatile int *)&(v)->counter);
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}
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static inline void atomic_set(atomic_t *v, int i)
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{
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v->counter = i;
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}
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#define atomic_get atomic_read
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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smp_mb();
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__asm__ __volatile__("@ atomic_add_return\n"
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"1: ldrex %0, [%3]\n"
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" add %0, %0, %4\n"
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" strex %1, %0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b\n"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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smp_mb();
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return result;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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smp_mb();
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__asm__ __volatile__("@ atomic_sub_return\n"
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"1: ldrex %0, [%3]\n"
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" sub %0, %0, %4\n"
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" strex %1, %0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b\n"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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smp_mb();
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return result;
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}
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static inline int atomic_inc(atomic_t *v) { return atomic_add_return(1, v) - 1; }
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static inline int atomic_add(int val, atomic_t *v) { return atomic_add_return(val, v) - val; }
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static inline int atomic_dec(atomic_t *v) { return atomic_sub_return(1, v) + 1; }
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/* true if the result is 0, or false for all other cases. */
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#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
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#define atomic_inc_return(v) (atomic_add_return(1, v))
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#endif /* __CR_ATOMIC_H__ */
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