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[trac813] a small update to the gen-wiredata script so that we can specify

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the textual RR class for TSIG rr_class.
This commit is contained in:
JINMEI Tatuya
2011-05-01 12:31:28 -07:00
parent e997ff18a6
commit 0261bbec3a
1 changed files with 4 additions and 3 deletions
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7
src/lib/dns/tests/testdata/gen-wiredata.py.in vendored
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@@ -435,7 +435,7 @@ class RRSIG:
class TSIG: class TSIG:
as_rr = False as_rr = False
rr_name = 'example.com' # only when as_rr is True, same for class/TTL rr_name = 'example.com' # only when as_rr is True, same for class/TTL
rr_class = parse_value('ANY', dict_rrclass) rr_class = 'ANY'
rr_ttl = 0 rr_ttl = 0
rdlen = None # auto-calculate rdlen = None # auto-calculate
@@ -477,12 +477,13 @@ class TSIG:
rdlen = int(len(name_wire) / 2 + 16 + len(mac) / 2 + \ rdlen = int(len(name_wire) / 2 + 16 + len(mac) / 2 + \
len(other_data) / 2) len(other_data) / 2)
if self.as_rr: if self.as_rr:
rrclass = parse_value(self.rr_class, dict_rrclass)
f.write('\n# TSIG RR (QNAME=%s Class=%s TTL=%d RDLEN=%d)\n' % f.write('\n# TSIG RR (QNAME=%s Class=%s TTL=%d RDLEN=%d)\n' %
(self.rr_name, rdict_rrclass[self.rr_class], (self.rr_name, code_totext(rrclass, rdict_rrclass),
self.rr_ttl, rdlen)) self.rr_ttl, rdlen))
f.write('%s %04x %04x %08x %04x\n' % f.write('%s %04x %04x %08x %04x\n' %
(encode_name(self.rr_name), dict_rrtype['tsig'], (encode_name(self.rr_name), dict_rrtype['tsig'],
self.rr_class, self.rr_ttl, rdlen)) rrclass, self.rr_ttl, rdlen))
else: else:
f.write('\n# TSIG RDATA (RDLEN=%d)\n' % rdlen) f.write('\n# TSIG RDATA (RDLEN=%d)\n' % rdlen)
f.write('%04x\n' % rdlen); f.write('%04x\n' % rdlen);