2
0
mirror of https://gitlab.isc.org/isc-projects/kea synced 2025-09-04 07:55:18 +00:00

[(no branch, rebasing 1880-implement-the-tkey-rr)] [(no branch, rebasing 1880-implement-the-tkey-rr)] [(no branch, rebasing 1880-implement-the-tkey-rr)] [#1880] Checkpoint: UT half done

This commit is contained in:
Francis Dupont
2021-05-25 20:50:32 +00:00
parent 77cdc5438f
commit ba3750b05b
17 changed files with 180 additions and 29 deletions

View File

@@ -161,7 +161,6 @@ TEST_F(Rdata_TKEY_Test, badText) {
// not enough fields
checkFromText_LexerError("foo 20210501120000 20210501130000 0 BADKEY");
// bad domain name
std::cerr << "checkFromText_TooLongLabel\n";
checkFromText_TooLongLabel(
"0123456789012345678901234567890123456789012345678901234567890123"
" 20210501120000 20210501130000 0 0 0 0");
@@ -235,18 +234,13 @@ TEST_F(Rdata_TKEY_Test, createFromWireWithOtherData) {
"rdata_tkey_fromWire2.wire"));
const generic::TKEY& tkey(dynamic_cast<generic::TKEY&>(*rdata));
////
#if 0
expect_data.resize(6);
expect_data[0] = (otherdata >> 40);
expect_data[1] = ((otherdata >> 32) & 0xff);
expect_data[2] = ((otherdata >> 24) & 0xff);
expect_data[3] = ((otherdata >> 16) & 0xff);
expect_data[4] = ((otherdata >> 8) & 0xff);
expect_data[5] = (otherdata & 0xff);
vector<uint8_t> expect_key(32, 'x');
matchWireData(&expect_key[0], expect_key.size(),
tkey.getKey(), tkey.getKeyLen());
vector<uint8_t> expect_data = { 'a', 'b', 'c', 'd', '0', '1', '2', '3' };
matchWireData(&expect_data[0], expect_data.size(),
tkey.getOtherData(), tkey.getOtherLen());
#endif
}
TEST_F(Rdata_TKEY_Test, createFromWireWithoutKey) {
@@ -255,6 +249,10 @@ TEST_F(Rdata_TKEY_Test, createFromWireWithoutKey) {
const generic::TKEY& tkey(dynamic_cast<generic::TKEY&>(*rdata));
EXPECT_EQ(0, tkey.getKeyLen());
EXPECT_EQ(static_cast<const void*>(0), tkey.getKey());
vector<uint8_t> expect_data = { 'a', 'b', 'c', 'd', '0', '1', '2', '3' };
matchWireData(&expect_data[0], expect_data.size(),
tkey.getOtherData(), tkey.getOtherLen());
}
TEST_F(Rdata_TKEY_Test, createFromWireWithCompression) {

View File

@@ -91,6 +91,14 @@ EXTRA_DIST += rrcode16_fromWire1 rrcode16_fromWire2
EXTRA_DIST += rrcode32_fromWire1 rrcode32_fromWire2
EXTRA_DIST += rrset_toWire1 rrset_toWire2
EXTRA_DIST += rrset_toWire3 rrset_toWire4
EXTRA_DIST += rdata_tkey_fromWire1.spec rdata_tkey_fromWire2.spec
EXTRA_DIST += rdata_tkey_fromWire3.spec rdata_tkey_fromWire4.spec
EXTRA_DIST += rdata_tkey_fromWire5.spec rdata_tkey_fromWire6.spec
EXTRA_DIST += rdata_tkey_fromWire7.spec rdata_tkey_fromWire8.spec
EXTRA_DIST += rdata_tkey_fromWire9.spec
EXTRA_DIST += rdata_tkey_toWire1.spec rdata_tkey_toWire2.spec
EXTRA_DIST += rdata_tkey_toWire3.spec rdata_tkey_toWire4.spec
EXTRA_DIST += rdata_tkey_toWire5.spec
EXTRA_DIST += rdata_tlsa_fromWire rdata_tlsa_fromWire2
EXTRA_DIST += rdata_tlsa_fromWire3.spec rdata_tlsa_fromWire4.spec
EXTRA_DIST += rdata_tlsa_fromWire5.spec rdata_tlsa_fromWire6.spec
@@ -189,6 +197,14 @@ EXTRA_DIST += rdata_tsig_toWire3.wire rdata_tsig_toWire4.wire
EXTRA_DIST += rdata_tsig_toWire5.wire
EXTRA_DIST += rdata_caa_fromWire1.wire rdata_caa_fromWire2.wire
EXTRA_DIST += rdata_caa_fromWire3.wire rdata_caa_fromWire4.wire
EXTRA_DIST += rdata_tkey_fromWire1.wire rdata_tkey_fromWire2.wire
EXTRA_DIST += rdata_tkey_fromWire3.wire rdata_tkey_fromWire4.wire
EXTRA_DIST += rdata_tkey_fromWire5.wire rdata_tkey_fromWire6.wire
EXTRA_DIST += rdata_tkey_fromWire7.wire rdata_tkey_fromWire8.wire
EXTRA_DIST += rdata_tkey_fromWire9.wire
EXTRA_DIST += rdata_tkey_toWire1.wire rdata_tkey_toWire2.wire
EXTRA_DIST += rdata_tkey_toWire3.wire rdata_tkey_toWire4.wire
EXTRA_DIST += rdata_tkey_toWire5.wire
EXTRA_DIST += tsigrecord_toWire1.wire tsigrecord_toWire2.wire
EXTRA_DIST += tsig_verify1.wire tsig_verify2.wire tsig_verify3.wire
EXTRA_DIST += tsig_verify4.wire tsig_verify5.wire tsig_verify6.wire

View File

@@ -0,0 +1,6 @@
#
# A simplest form of TKEY: all default parameters
#
[custom]
sections: tkey
[tkey]

View File

@@ -0,0 +1,8 @@
#
# TKEY with other data
#
[custom]
sections: tkey
[tkey]
other_len: 8
other_data: abcd0123

View File

@@ -0,0 +1,9 @@
#
# TKEY without Key
#
[custom]
sections: tkey
[tkey]
key_len: 0
other_len: 8
other_data: abcd0123

View File

@@ -0,0 +1,11 @@
#
# A simplest form of TKEY, but the algorithm name is compressed (quite
# pathological, but we accept it)
#
[custom]
sections: name:tkey
[name]
name: gss-tsig
[tkey]
algorithm: ptr=0
key_len: 32

View File

@@ -0,0 +1,7 @@
#
# TSIG-like RDATA but RDLEN is too short.
#
[custom]
sections: tsig
[tsig]
rdlen: 60

View File

@@ -0,0 +1,7 @@
#
# TSIG-like RDATA but RDLEN is too long.
#
[custom]
sections: tsig
[tsig]
rdlen: 63

View File

@@ -0,0 +1,8 @@
#
# TSIG-like RDATA but algorithm name is broken.
#
[custom]
sections: tsig
[tsig]
algorithm: "01234567890123456789012345678901234567890123456789012345678901234"
mac_size: 32

View File

@@ -0,0 +1,8 @@
#
# TSIG-like RDATA but MAC size is bogus
#
[custom]
sections: tsig
[tsig]
mac_size: 65535
mac: "dummy data"

View File

@@ -0,0 +1,8 @@
#
# TSIG-like RDATA but Other-Data length is bogus
#
[custom]
sections: tsig
[tsig]
other_len: 65535
otherdata: "dummy data"

View File

@@ -0,0 +1,11 @@
#
# An artificial TSIG RDATA for toWire test.
#
[custom]
sections: tsig
[tsig]
algorithm: hmac-md5
time_signed: 1286779327
mac_size: 0
original_id: 16020
error: 17

View File

@@ -0,0 +1,13 @@
#
# An artificial TSIG RDATA for toWire test.
#
[custom]
sections: tsig
[tsig]
algorithm: hmac-sha256
time_signed: 1286779327
mac_size: 12
# 0x1402... would be FAKEFAKE... if encoded in BASE64
mac: 0x140284140284140284140284
original_id: 16020
error: 16

View File

@@ -0,0 +1,15 @@
#
# An artificial TSIG RDATA for toWire test.
#
[custom]
sections: tsig
[tsig]
algorithm: hmac-sha1
time_signed: 1286779327
mac_size: 12
# 0x1402... would be FAKEFAKE... if encoded in BASE64
mac: 0x140284140284140284140284
original_id: 16020
error: 18
other_len: 6
other_data: 0x140284140284

View File

@@ -0,0 +1,13 @@
#
# An artificial TSIG RDATA for toWire test.
#
[custom]
sections: name:tsig
[name]
name: hmac-md5.sig-alg.reg.int.
[tsig]
algorithm: hmac-md5
time_signed: 1286779327
mac_size: 0
original_id: 16020
error: 17

View File

@@ -0,0 +1,13 @@
#
# An artificial TSIG RDATA for toWire test.
#
[custom]
sections: tsig:name
[tsig]
algorithm: hmac-md5
time_signed: 1286779327
mac_size: 0
original_id: 16020
error: 17
[name]
name: ptr=2

View File

@@ -1190,7 +1190,7 @@ class TKEY(RR):
generally interpreted as a domain name string, and will
typically be gss-tsig.
- inception (32-bit int): The Inception TTL field.
- expiration (32-bit int): The Expiration TTL field.
- expire (32-bit int): The Expire TTL field.
- mode (16-bit int): The Mode field.
- error (16-bit int): The Error field.
- key_len (int): The Key Len field.
@@ -1210,16 +1210,16 @@ class TKEY(RR):
'''
algorithm = 'gss-tsig'
inception = int(time.mktime(datetime.strptime('20210501130000',
inception = int(time.mktime(datetime.strptime('20210501120000',
dnssec_timefmt).timetuple()))
expiration = int(time.mktime(datetime.strptime('20210501130000',
expire = int(time.mktime(datetime.strptime('20210501130000',
dnssec_timefmt).timetuple()))
mode = 3 # GSS-API
error = 0
key_len = None
key = None # use 'x' *
other_len = None
other_data = None # same as key
key_len = 32
key = None # use 'x' * key_len
other_len = 0
other_data = None
# TKEY has some special defaults
def __init__(self):
@@ -1230,11 +1230,9 @@ class TKEY(RR):
def dump(self, f):
name_wire = encode_name(self.algorithm)
key_len = self.key_len
if key_len is None:
key_len = 0
key = self.key
if key is None:
key = ''
key = encode_string('x' * key_len)
else:
key = encode_string(self.key, key_len)
other_len = self.other_len
@@ -1242,17 +1240,19 @@ class TKEY(RR):
other_len = 0
other_data = self.other_data
if other_data is None:
other_data = ''
else:
other_data = encode_string(self.other_data, other_len)
if self.rdlen is None:
self.rdlen = int(len(name_wire) / 2 + 12 + len(mac) / 2 + \
self.rdlen = int(len(name_wire) / 2 + 16 + len(key) / 2 + \
len(other_data) / 2)
self.dump_header(f, self.rdlen)
f.write('# Algorithm=%s Inception=%d Expire=%d Mode=%d Error=%d\n' %
(self.algorithm, self.inception, self.expire,
self.mode, self.error))
f.write('%s %08x %08x %04x %04x\n' %
(self.algorithm, self.inception, self.expire,
self.mode, self.error))
f.write('# Algorithm=%s\n' % self.algorithm)
f.write('%s\n' % name_wire)
f.write('# Inception=%d Expire=%d Mode=%d Error=%d\n' %
(self.inception, self.expire, self.mode, self.error))
f.write('%08x %08x %04x %04x\n' %
(self.inception, self.expire, self.mode, self.error))
f.write('# Key Len=%d Key=(see hex)\n' % key_len)
f.write('%04x%s\n' % (key_len, ' ' + key if len(key) > 0 else ''))
f.write('# Other-Len=%d Other-Data=(see hex)\n' % other_len)