1998-12-15 04:55:51 +00:00
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#!/usr/bin/perl
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#
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1999-02-08 22:50:29 +00:00
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# Copyright 1998, 1999 Philip Edelbrock <phil@netroedge.com>
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2000-09-21 02:24:30 +00:00
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# modified by Christian Zuckschwerdt <zany@triq.net>
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1998-12-15 04:55:51 +00:00
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#
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2000-09-21 02:27:21 +00:00
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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#
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2000-09-21 02:24:30 +00:00
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# Version 0.4 1999 Philip Edelbrock <phil@netroedge.com>
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# Version 0.5 2000-03-30 Christian Zuckschwerdt <zany@triq.net>
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# html output (selectable by commandline switches)
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# Version 0.6 2000-09-16 Christian Zuckschwerdt <zany@triq.net>
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# updated according to SPD Spec Rev 1.2B
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# see http://developer.intel.com/
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# technology/memory/pc133sdram/spec/Spdsd12b.htm
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1998-12-15 04:55:51 +00:00
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#
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# EEPROM data decoding for SDRAM DIMM modules.
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#
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2000-09-21 02:24:30 +00:00
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# Two assumptions: lm_sensors-2.x installed,
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1998-12-15 04:55:51 +00:00
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# and Perl is at /usr/bin/perl
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#
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2000-09-21 02:24:30 +00:00
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# use the following command line switches
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# -f, --format print nice html output
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# -b, --bodyonly don't printhtml header
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# (useful for postprocessing the output)
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# -h, --help display this usage summary
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1998-12-15 04:55:51 +00:00
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#
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1998-12-20 07:48:16 +00:00
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# References:
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# PC SDRAM Serial Presence
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1998-12-15 04:55:51 +00:00
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# Detect (SPD) Specification, Intel,
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2000-09-21 02:24:30 +00:00
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# 1997,1999, Rev 1.2B
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1998-12-20 07:48:16 +00:00
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#
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# Jedec Standards 4.1.x & 4.5.x
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# http://www.jedec.org
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#
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1998-12-15 04:55:51 +00:00
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2000-09-21 02:24:30 +00:00
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sub printl ($$) # print a line w/ label and value
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{
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my ($label, $value) = @_;
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if ($opt_html) {
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$value =~ s%\n%<br>%sg;
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print "<tr><td valign=top>$label</td><td>$value</td></tr>\n";
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} else {
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$value =~ s%\n%\n\t\t%sg;
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print "$label\t$value\n";
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}
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}
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sub prints ($) # print seperator w/ given text
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{
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my ($label) = @_;
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if ($opt_html) {
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print "<tr><td align=center colspan=2><b>$label</b></td></tr>\n";
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} else {
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print "\n---=== $label ===---\n";
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}
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}
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sub printh ($) # print header w/ given text
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{
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my ($label) = @_;
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if ($opt_html) {
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$label =~ s%\n%<br>%sg;
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print "<h1>$label</h1>\n";
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} else {
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print "\n$label\n";
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}
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}
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for (@ARGV) {
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if (/-h/) {
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print "Usage: $0 [-f|-b|-h]
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-f, --format print nice html output
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-b, --bodyonly don't printhtml header
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(useful for postprocessing the output)
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-h, --help display this usage summary
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";
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exit;
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}
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$opt_html = 1 if (/-f/);
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$opt_bodyonly = 1 if (/-b/);
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}
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$opt_body = $opt_html and not $opt_bodyonly;
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print "<html><head></head><body>\n" if $opt_body;
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printh '
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PC DIMM Serial Presence Detect Tester/Decoder
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Written by Philip Edelbrock. Copyright 1998, 1999.
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Modified by Christian Zuckschwerdt <zany@triq.net>
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Version 0.6
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';
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print "<table border=1>\n" if $opt_html;
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1998-12-15 04:55:51 +00:00
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$dimm_count=0;
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$_=`ls /proc/sys/dev/sensors/`;
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@dimm_list=split();
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for $i ( 0 .. $#dimm_list ) {
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$_=$dimm_list[$i];
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if (/^eeprom-/) {
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1998-12-20 07:48:16 +00:00
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$dimm_checksum=0;
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1998-12-15 04:55:51 +00:00
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$dimm_count=$dimm_count + 1;
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2000-09-21 02:24:30 +00:00
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printl "Decoding EEPROM", "/proc/sys/dev/sensors/$dimm_list[$i]";
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1998-12-15 04:55:51 +00:00
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if (/^[^-]+-[^-]+-[^-]+-([^-]+)$/) {
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$dimm_num=$1 - 49;
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2000-09-21 02:24:30 +00:00
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printl "Guessing DIMM is in", "bank $dimm_num";
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1998-12-15 04:55:51 +00:00
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}
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# Decode first 16 bytes
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2000-09-21 02:24:30 +00:00
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prints "The Following is Required Data and is Applicable to all DIMM Types";
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1998-12-15 04:55:51 +00:00
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$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data0-15`;
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@bytes=split(" ");
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1998-12-20 07:48:16 +00:00
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for $j ( 0 .. 15 ) { $dimm_checksum = $dimm_checksum + $bytes[$j]; }
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2000-09-21 02:24:30 +00:00
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printl "# of bytes written to SDRAM EEPROM",$bytes[0];
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1998-12-15 04:55:51 +00:00
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2000-09-21 02:24:30 +00:00
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$l = "Total number of bytes in EEPROM";
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if ($bytes[1] <= 13) {
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printl $l, 2**$bytes[1];
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1998-12-15 04:55:51 +00:00
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} elsif ($bytes[1] == 0) {
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2000-09-21 02:24:30 +00:00
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printl $l, "RFU";
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} else { printl $l, "ERROR!"; }
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1998-12-15 04:55:51 +00:00
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2000-09-21 02:24:30 +00:00
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$l = "Fundemental Memory type";
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if ($bytes[2] == 2) { printl $l, "EDO"; }
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elsif ($bytes[2] == 4) { printl $l, "SDRAM"; }
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else { printl $l, "???"; }
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1998-12-15 04:55:51 +00:00
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2000-09-21 02:24:30 +00:00
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$l = "Number of Row Address Bits (SDRAM only)";
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if ($bytes[3] == 0) { printl $l, "Undefined!" }
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elsif ($bytes[3] == 1) { printl $l, "1/16" }
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elsif ($bytes[3] == 2) { printl $l, "2/17" }
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elsif ($bytes[3] == 3) { printl $l, "3/18" }
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else { printl $l, $bytes[3]; }
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1998-12-15 04:55:51 +00:00
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2000-09-21 02:24:30 +00:00
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$l = "Number of Col Address Bits (SDRAM only)";
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if ($bytes[4] == 0) { printl $l, "Undefined!" }
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elsif ($bytes[4] == 1) { printl $l, "1/16" }
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elsif ($bytes[4] == 2) { printl $l, "2/17" }
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elsif ($bytes[4] == 3) { printl $l, "3/18" }
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else { printl $l, $bytes[4]; }
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1998-12-15 04:55:51 +00:00
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2000-09-21 02:24:30 +00:00
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$l = "Number of Module Rows";
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if ($bytes[5] == 0 ) { printl $l, "Undefined!"; }
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else { printl $l, $bytes[5]; }
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1998-12-15 04:55:51 +00:00
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2000-09-21 02:24:30 +00:00
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$l = "Data Width (SDRAM only)";
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if ($bytes[7] > 1) { printl $l, "Undefined!" } else {
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1998-12-15 04:55:51 +00:00
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$temp=($bytes[7]*256) + $bytes[6];
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2000-09-21 02:24:30 +00:00
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printl $l, $temp; }
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1998-12-15 04:55:51 +00:00
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2000-09-21 02:24:30 +00:00
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$l = "Module Interface Signal Levels";
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if ($bytes[8] == 0) { printl $l, "5.0 Volt/TTL";}
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elsif ($bytes[8] == 1) { printl $l, "LVTTL";}
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elsif ($bytes[8] == 2) { printl $l, "HSTL 1.5";}
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elsif ($bytes[8] == 3) { printl $l, "SSTL 3.3";}
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elsif ($bytes[8] == 4) { printl $l, "SSTL 2.5";}
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elsif ($bytes[8] == 255) { printl $l, "New Table";}
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else { printl $l, "Undefined!";}
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$l = "Cycle Time (SDRAM) highest CAS latency";
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$temp=($bytes[9] >> 4) + ($bytes[9] & 0xf) * 0.1;
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printl $l, "${temp}ns";
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$l = "Access Time (SDRAM)";
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$temp=($bytes[10] >> 4) + ($bytes[10] & 0xf) * 0.1;
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printl $l, "${temp}ns";
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$l = "Module Configuration Type";
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if ($bytes[11] == 0) { printl $l, "No Parity"; }
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elsif ($bytes[11] == 1) { printl $l, "Parity"; }
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elsif ($bytes[11] == 2) { printl $l, "ECC"; }
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else { printl $l, "Undefined!"; }
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1998-12-15 04:55:51 +00:00
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2000-09-21 02:24:30 +00:00
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$l = "Refresh Type";
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if ($bytes[12] > 126) { printl $l, "Self Refreshing"; }
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else { printl $l, "Not Self Refreshing"; }
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$l = "Refresh Rate";
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$temp=$bytes[12] & 0x7f;
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if ($temp == 0) { printl $l, "Normal (15.625uS)"; }
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elsif ($temp == 1) { printl $l, "Reduced (3.9uS)"; }
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elsif ($temp == 2) { printl $l, "Reduced (7.8uS)"; }
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elsif ($temp == 3) { printl $l, "Extended (31.3uS)"; }
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elsif ($temp == 4) { printl $l, "Extended (62.5uS)"; }
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elsif ($temp == 5) { printl $l, "Extended (125uS)"; }
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else { printl $l, "Undefined!";}
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$l = "Primary SDRAM Component Bank Config";
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if ($bytes[13]>126) { printl $l, "Bank2 = 2 x Bank1";}
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else { printl $l, "No Bank2 OR Bank2 = Bank1 width";}
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$l = "Primary SDRAM Component Widths";
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$temp=$bytes[13] & 0x7f;
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if ($temp == 0) { printl $l, "Undefined!\n"; }
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else { printl $l, $temp; }
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$l = "Error Checking SDRAM Component Bank Config";
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if ($bytes[14]>126) { printl $l, "Bank2 = 2 x Bank1";}
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else { printl $l, "No Bank2 OR Bank2 = Bank1 width";}
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$l = "Error Checking SDRAM Component Widths";
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$temp=$bytes[14] & 0x7f;
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if ($temp == 0) { printl $l, "Undefined!"; }
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else { printl $l, $temp; }
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$l = "Min Clock Delay for Back to Back Random Access";
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if ($bytes[15] == 0) { printl $l, "Undefined!"; }
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else { printl $l, $bytes[15]; }
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prints "The Following Apply to SDRAM DIMMs ONLY";
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1998-12-15 04:55:51 +00:00
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# Decode next 16 bytes
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$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data16-31`;
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@bytes=split(" ");
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2000-09-21 02:24:30 +00:00
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for $j ( 0 .. 15 ) { $dimm_checksum = $dimm_checksum + $bytes[$j]; }
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1998-12-15 04:55:51 +00:00
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2000-09-21 02:24:30 +00:00
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$l = "Burst lengths supported";
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1998-12-15 04:55:51 +00:00
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$temp="";
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2000-09-21 02:24:30 +00:00
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if (($bytes[0] & 1) > 0) { $temp .= "Burst Length = 1\n"; }
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if (($bytes[0] & 2) > 0) { $temp .= "Burst Length = 2\n"; }
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if (($bytes[0] & 4) > 0) { $temp .= "Burst Length = 4\n"; }
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if (($bytes[0] & 8) > 0) { $temp .= "Burst Length = 8\n"; }
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if (($bytes[0] & 16) > 0) { $temp .= "Undefined! (bit 4)\n"; }
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if (($bytes[0] & 32) > 0) { $temp .= "Undefined! (bit 5)\n"; }
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if (($bytes[0] & 64) > 0) { $temp .= "Undefined! (bit 6)\n"; }
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if (($bytes[0] & 128) > 0) { $temp .= "Burst Length = Page\n"; }
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if ($bytes[0] == 0) { $temp .= "(None Supported)\n";}
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printl $l, $temp;
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$l = "Number of Device Banks";
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if ($bytes[1] == 0) { printl $l, "Undefined/Reserved!"; }
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else { printl $l, $bytes[1]; }
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$l = "Supported CAS Latencies";
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1998-12-15 04:55:51 +00:00
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$temp="";
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2000-09-21 02:24:30 +00:00
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if (($bytes[2] & 1) > 0) { $temp .= "CAS Latency = 1\n";}
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if (($bytes[2] & 2) > 0) { $temp .= "CAS Latency = 2\n"; }
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if (($bytes[2] & 4) > 0) { $temp .= "CAS Latency = 3\n"; }
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if (($bytes[2] & 8) > 0) { $temp .= "CAS Latency = 4\n"; }
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if (($bytes[2] & 16) > 0) { $temp .= "CAS Latency = 5\n"; }
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if (($bytes[2] & 32) > 0) { $temp .= "CAS Latency = 6\n"; }
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if (($bytes[2] & 64) > 0) { $temp .= "CAS Latency = 7\n"; }
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if (($bytes[2] & 128) > 0) { $temp .= "Undefined (bit 7)\n"; }
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if ($bytes[2] == 0) { $temp .= "(None Supported)\n";}
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printl $l, $temp;
|
|
|
|
|
|
|
|
|
|
$l = "Supported CS Latencies";
|
1998-12-15 04:55:51 +00:00
|
|
|
$temp="";
|
2000-09-21 02:24:30 +00:00
|
|
|
if (($bytes[3] & 1) > 0) { $temp .= "CS Latency = 0\n";}
|
|
|
|
|
if (($bytes[3] & 2) > 0) { $temp .= "CS Latency = 1\n"; }
|
|
|
|
|
if (($bytes[3] & 4) > 0) { $temp .= "CS Latency = 2\n"; }
|
|
|
|
|
if (($bytes[3] & 8) > 0) { $temp .= "CS Latency = 3\n"; }
|
|
|
|
|
if (($bytes[3] & 16) > 0) { $temp .= "CS Latency = 4\n"; }
|
|
|
|
|
if (($bytes[3] & 32) > 0) { $temp .= "CS Latency = 5\n"; }
|
|
|
|
|
if (($bytes[3] & 64) > 0) { $temp .= "CS Latency = 6\n"; }
|
|
|
|
|
if (($bytes[3] & 128) > 0) { $temp .= "Undefined (bit 7)\n"; }
|
|
|
|
|
if ($bytes[3] == 0) { $temp .= "(None Supported)\n";}
|
|
|
|
|
printl $l, $temp;
|
|
|
|
|
|
|
|
|
|
$l = "Supported WE Latencies";
|
1998-12-15 04:55:51 +00:00
|
|
|
$temp="";
|
2000-09-21 02:24:30 +00:00
|
|
|
if (($bytes[4] & 1) > 0) { $temp .= "WE Latency = 0\n";}
|
|
|
|
|
if (($bytes[4] & 2) > 0) { $temp .= "WE Latency = 1\n"; }
|
|
|
|
|
if (($bytes[4] & 4) > 0) { $temp .= "WE Latency = 2\n"; }
|
|
|
|
|
if (($bytes[4] & 8) > 0) { $temp .= "WE Latency = 3\n"; }
|
|
|
|
|
if (($bytes[4] & 16) > 0) { $temp .= "WE Latency = 4\n"; }
|
|
|
|
|
if (($bytes[4] & 32) > 0) { $temp .= "WE Latency = 5\n"; }
|
|
|
|
|
if (($bytes[4] & 64) > 0) { $temp .= "WE Latency = 6\n"; }
|
|
|
|
|
if (($bytes[4] & 128) > 0) { $temp .= "Undefined (bit 7)\n"; }
|
|
|
|
|
if ($bytes[4] == 0) { $temp .= "(None Supported)\n";}
|
|
|
|
|
printl $l, $temp;
|
|
|
|
|
|
|
|
|
|
$l = "SDRAM Module Attributes";
|
1998-12-15 04:55:51 +00:00
|
|
|
$temp="";
|
2000-09-21 02:24:30 +00:00
|
|
|
if (($bytes[5] & 1) > 0) { $temp .= "Buffered Address/Control Inputs\n";}
|
|
|
|
|
if (($bytes[5] & 2) > 0) { $temp .= "Registered Address/Control Inputs\n"; }
|
|
|
|
|
if (($bytes[5] & 4) > 0) { $temp .= "On card PLL (clock)\n"; }
|
|
|
|
|
if (($bytes[5] & 8) > 0) { $temp .= "Buffered DQMB Inputs\n"; }
|
|
|
|
|
if (($bytes[5] & 16) > 0) { $temp .= "Registered DQMB Inputs\n"; }
|
|
|
|
|
if (($bytes[5] & 32) > 0) { $temp .= "Differential Clock Input\n"; }
|
|
|
|
|
if (($bytes[5] & 64) > 0) { $temp .= "Redundant Row Address\n"; }
|
|
|
|
|
if (($bytes[5] & 128) > 0) { $temp .= "Undefined (bit 7)\n"; }
|
|
|
|
|
if ($bytes[5] == 0) { $temp .= "(None Reported)\n";}
|
|
|
|
|
printl $l, $temp;
|
|
|
|
|
|
|
|
|
|
$l = "SDRAM Device Attributes (General)";
|
1998-12-15 04:55:51 +00:00
|
|
|
$temp="";
|
2000-09-21 02:24:30 +00:00
|
|
|
if (($bytes[6] & 1) > 0) { $temp .= "Supports Early RAS# Recharge\n";}
|
|
|
|
|
if (($bytes[6] & 2) > 0) { $temp .= "Supports Auto-Precharge\n"; }
|
|
|
|
|
if (($bytes[6] & 4) > 0) { $temp .= "Supports Precharge All\n"; }
|
|
|
|
|
if (($bytes[6] & 8) > 0) { $temp .= "Supports Write1/Read Burst\n"; }
|
|
|
|
|
if (($bytes[6] & 16) > 0) { $temp .= "Lower VCC Tolerance:5%\n"; }
|
|
|
|
|
if (($bytes[6] & 16) == 0) { $temp .= "Lower VCC Tolerance:10%\n"; }
|
|
|
|
|
if (($bytes[6] & 32) > 0) { $temp .= "Upper VCC Tolerance:5%\n"; }
|
|
|
|
|
if (($bytes[6] & 32) == 0) { $temp .= "Upper VCC Tolerance:10%\n"; }
|
|
|
|
|
if (($bytes[6] & 64) > 0) { $temp .= "Undefined (bit 6)\n"; }
|
|
|
|
|
if (($bytes[6] & 128) > 0) { $temp .= "Undefined (bit 7)\n"; }
|
|
|
|
|
printl $l, $temp;
|
|
|
|
|
|
|
|
|
|
$l = "SDRAM Cycle Time (2nd highest CAS)";
|
|
|
|
|
$temp = $bytes[7] >> 4;
|
|
|
|
|
if ($temp == 0) { printl $l, "Undefined!"; }
|
|
|
|
|
else {
|
1998-12-15 04:55:51 +00:00
|
|
|
if ($temp < 4 ) {$temp=$temp + 15;}
|
2000-09-21 02:24:30 +00:00
|
|
|
printl $l, $temp + (($bytes[7] & 0xf) * 0.1) . "nS";
|
1998-12-15 04:55:51 +00:00
|
|
|
}
|
|
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "SDRAM Access from Clock Time (2nd highest CAS)";
|
|
|
|
|
$temp = $bytes[8] >> 4;
|
|
|
|
|
if ($temp == 0) { printl $l, "Undefined!"; }
|
|
|
|
|
else {
|
1998-12-15 04:55:51 +00:00
|
|
|
if ($temp < 4 ) {$temp=$temp + 15;}
|
2000-09-21 02:24:30 +00:00
|
|
|
printl $l, $temp + (($bytes[8] & 0xf) * 0.1) . "nS";
|
1998-12-15 04:55:51 +00:00
|
|
|
}
|
|
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
prints "The Following are Optional (may be Bogus)";
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "SDRAM Cycle Time (3rd highest CAS)";
|
|
|
|
|
$temp = $bytes[9] >> 2;
|
|
|
|
|
if ($temp == 0) { printl $l, "Undefined!"; }
|
|
|
|
|
else { printl $l, $temp + ($bytes[9] & 0x3) * 0.25 . "nS"; }
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "SDRAM Access from Clock Time (3rd highest CAS)";
|
|
|
|
|
$temp = $bytes[10] >> 2;
|
|
|
|
|
if ($temp == 0) { printl $l, "Undefined!"; }
|
|
|
|
|
else { printl $l, $temp + ($bytes[10] & 0x3) * 0.25 . "nS"; }
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
prints "The Following are Required (for SDRAMs)";
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Minumum Row Precharge Time";
|
|
|
|
|
if ($bytes[11] == 0) { printl $l, "Undefined!"; }
|
|
|
|
|
else { printl $l, "$bytes[11]nS"; }
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Row Active to Row Active Min";
|
|
|
|
|
if ($bytes[12] == 0) { printl $l, "Undefined!"; }
|
|
|
|
|
else { printl $l, "$bytes[12]nS"; }
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "RAS to CAS Delay";
|
|
|
|
|
if ($bytes[13] == 0) { printl $l, "Undefined!"; }
|
|
|
|
|
else { printl $l, "$bytes[13]nS"; }
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Min RAS Pulse Width";
|
|
|
|
|
if ($bytes[14] == 0) { printl $l, "Undefined!"; }
|
|
|
|
|
else { printl $l, "$bytes[14]nS"; }
|
1998-12-15 04:55:51 +00:00
|
|
|
|
|
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
prints "The Following are Required and Apply to ALL DIMMs";
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Row Densities";
|
1998-12-15 04:55:51 +00:00
|
|
|
$temp="";
|
2000-09-21 02:24:30 +00:00
|
|
|
if (($bytes[15] & 1) > 0) { $temp .= "4 MByte\n";}
|
|
|
|
|
if (($bytes[15] & 2) > 0) { $temp .= "8 MByte\n"; }
|
|
|
|
|
if (($bytes[15] & 4) > 0) { $temp .= "16 MByte\n"; }
|
|
|
|
|
if (($bytes[15] & 8) > 0) { $temp .= "32 MByte\n"; }
|
|
|
|
|
if (($bytes[15] & 16) > 0) { $temp .= "64 MByte\n"; }
|
|
|
|
|
if (($bytes[15] & 32) > 0) { $temp .= "128 MByte\n"; }
|
|
|
|
|
if (($bytes[15] & 64) > 0) { $temp .= "256 MByte\n"; }
|
|
|
|
|
if (($bytes[15] & 128) > 0) { $temp .= "512 MByte\n"; }
|
|
|
|
|
if ($bytes[15] == 0) { $temp .= "(Undefined! -- None Reported!)\n";}
|
|
|
|
|
printl $l, $temp;
|
1998-12-15 04:55:51 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
# Decode next 16 bytes (32-47)
|
|
|
|
|
$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data32-47`;
|
|
|
|
|
@bytes=split(" ");
|
1998-12-20 07:48:16 +00:00
|
|
|
for $j ( 0 .. 15 ) { $dimm_checksum = $dimm_checksum + $bytes[$j]; }
|
|
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
prints "The Following are Proposed and Apply to SDRAM DIMMs";
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Command and Address Signal Setup Time";
|
|
|
|
|
$temp = (($bytes[0] & 0x7f) >> 4) + ($bytes[0] & 0xf) * 0.1;
|
|
|
|
|
printl $l, ( ($bytes[0] >> 7) ? -$temp : $temp ) . "nS";
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Command and Address Signal Hold Time";
|
|
|
|
|
$temp = (($bytes[1] & 0x7f) >> 4) + ($bytes[1] & 0xf) * 0.1;
|
|
|
|
|
printl $l, ( ($bytes[1] >> 7) ? -$temp : $temp ) . "nS";
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Data Signal Setup Time";
|
|
|
|
|
$temp =(($bytes[2] & 0x7f) >> 4) + ($bytes[2] & 0xf) * 0.1;
|
|
|
|
|
printl $l, ( ($bytes[2] >> 7) ? -$temp : $temp ) . "nS";
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Data Signal Hold Time";
|
|
|
|
|
$temp = (($bytes[3] & 0x7f) >> 4) + ($bytes[3] & 0xf) * 0.1;
|
|
|
|
|
printl $l, ( ($bytes[3] >> 7) ? -$temp : $temp ) . "nS";
|
1998-12-15 04:55:51 +00:00
|
|
|
|
|
|
|
|
# That's it for the lower part of an SDRAM EEPROM's memory!
|
1998-12-20 07:48:16 +00:00
|
|
|
# Decode next 16 bytes (48-63)
|
|
|
|
|
$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data48-63`;
|
|
|
|
|
@bytes=split(" ");
|
|
|
|
|
for $j ( 0 .. 14 ) { $dimm_checksum = $dimm_checksum + $bytes[$j]; }
|
1998-12-15 04:55:51 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
printl "SPD Revision code ", sprintf("%x", $bytes[14]);
|
|
|
|
|
$l = "EEPROM Checksum of bytes 0-62";
|
|
|
|
|
$temp = sprintf("0x%.2X (verses calculated: 0x%.2X)\n",$bytes[15],$dimm_checksum & 255);
|
|
|
|
|
printl $l, $temp;
|
|
|
|
|
|
1998-12-20 07:48:16 +00:00
|
|
|
# Decode next 16 bytes (64-79)
|
|
|
|
|
$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data64-79`;
|
|
|
|
|
@bytes=split(" ");
|
|
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Manufacturer's JEDEC ID Code";
|
|
|
|
|
$temp = sprintf("0x%.2X%.2X%.2X%.2X%.2X%.2X%.2X%.2X\n",$bytes[0],$bytes[1],$bytes[2],$bytes[3],$bytes[4],$bytes[5],$bytes[6],$bytes[7]);
|
|
|
|
|
printl $l, $temp;
|
|
|
|
|
$temp = pack("cccccccc",
|
1999-08-23 00:14:56 +00:00
|
|
|
$bytes[0],$bytes[1],$bytes[2],$bytes[3],$bytes[4],$bytes[5],$bytes[6],$bytes[7]);
|
2000-09-21 02:24:30 +00:00
|
|
|
printl $l, "(\"$temp\")";
|
1998-12-20 07:48:16 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Manufacturing Location Code";
|
|
|
|
|
$temp = sprintf("0x%.2X\n",$bytes[8]);
|
|
|
|
|
printl $l, $temp;
|
1998-12-20 07:48:16 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Manufacurer's Part Number:\"";
|
1998-12-20 07:48:16 +00:00
|
|
|
# Decode next 16 bytes (80-95)
|
|
|
|
|
$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data80-95`;
|
|
|
|
|
@bytes2=split(" ");
|
2000-09-21 02:24:30 +00:00
|
|
|
$temp = pack("cccccccccccccccccc",$bytes[9],$bytes[10],$bytes[11],$bytes[12],$bytes[13],$bytes[14],$bytes[15],
|
1998-12-20 07:48:16 +00:00
|
|
|
$bytes2[0],$bytes2[1],$bytes2[2],$bytes2[3],$bytes2[4],$bytes2[5],$bytes2[6],$bytes2[7],$bytes2[8],$bytes2[9]);
|
2000-09-21 02:24:30 +00:00
|
|
|
printl $l, $temp;
|
1998-12-20 07:48:16 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Revision Code";
|
|
|
|
|
$temp = sprintf("0x%.2X%.2X\n",$bytes2[10],$bytes2[11]);
|
|
|
|
|
printl $l, $temp;
|
1998-12-20 07:48:16 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Manufacturing Date";
|
|
|
|
|
$temp = sprintf("0x%.2X%.2X\n",$bytes2[12],$bytes2[13]);
|
|
|
|
|
printl $l, $temp;
|
1998-12-20 07:48:16 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Assembly Serial Number";
|
1998-12-20 07:48:16 +00:00
|
|
|
# Decode next 16 bytes (96-111)
|
|
|
|
|
$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data96-111`;
|
|
|
|
|
@bytes=split(" ");
|
|
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$temp = sprintf("0x%.2X%.2X%.2X%.2X\n",$bytes2[15],$bytes[0],$bytes[1],$bytes[2]);
|
1998-12-20 07:48:16 +00:00
|
|
|
# Decode next 16 bytes (112-127)
|
|
|
|
|
$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data112-127`;
|
|
|
|
|
@bytes=split(" ");
|
|
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Intel Specification for Frequency";
|
|
|
|
|
if ($bytes[14] == 102) { printl $l, "66MHz\n"; }
|
|
|
|
|
elsif ($bytes[14] == 100) { printl $l, "100MHz\n"; }
|
|
|
|
|
else { printl $l, "Undefined!\n"; }
|
1998-12-20 07:48:16 +00:00
|
|
|
|
2000-09-21 02:24:30 +00:00
|
|
|
$l = "Intel Spec Details for 100MHz Support";
|
1998-12-20 07:48:16 +00:00
|
|
|
$temp="";
|
2000-09-21 02:24:30 +00:00
|
|
|
if (($bytes[15] & 1) > 0) { $temp .= "Intel Concurrent AutoPrecharge\n";}
|
|
|
|
|
if (($bytes[15] & 2) > 0) { $temp .= "CAS Latency = 2\n";}
|
|
|
|
|
if (($bytes[15] & 4) > 0) { $temp .= "CAS Latency = 3\n";}
|
|
|
|
|
if (($bytes[15] & 8) > 0) { $temp .= "Junction Temp A (90 degrees C)\n";}
|
|
|
|
|
if (($bytes[15] & 8) == 0) { $temp .= "Junction Temp B (100 degrees C)\n";}
|
|
|
|
|
if (($bytes[15] & 16) > 0) { $temp .= "CLK 3 Connected\n";}
|
|
|
|
|
if (($bytes[15] & 32) > 0) { $temp .= "CLK 2 Connected\n";}
|
|
|
|
|
if (($bytes[15] & 64) > 0) { $temp .= "CLK 1 Connected\n";}
|
|
|
|
|
if (($bytes[15] & 128) > 0) { $temp .= "CLK 0 Connected\n";}
|
|
|
|
|
if ($bytes[15] > 175) { $temp .= "Double Sided DIMM\n"; }
|
|
|
|
|
else { $temp .= "Single Sided DIMM\n";}
|
|
|
|
|
printl $l, $temp;
|
1998-12-20 07:48:16 +00:00
|
|
|
|
|
|
|
|
|
1998-12-15 04:55:51 +00:00
|
|
|
}
|
|
|
|
|
}
|
2000-09-21 02:24:30 +00:00
|
|
|
printl "Number of SDRAM DIMMs detected and decoded", $dimm_count;
|
|
|
|
|
|
|
|
|
|
print "</table>\n" if $opt_html;
|
|
|
|
|
print "</body></html>\n" if $opt_body;
|
|
|
|
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print "\nTry '$0 --format' for html output.\n" unless $opt_html;
|
