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Added initial support for Intel Sandy Bridge CPUs.

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This commit is contained in:
Michael Möller
2011-01-21 21:41:14 +00:00
parent 60c28cc250
commit b193ab9b43
1 changed files with 29 additions and 13 deletions
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42
Hardware/CPU/IntelCPU.cs
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@@ -46,7 +46,8 @@ namespace OpenHardwareMonitor.Hardware.CPU {
Unknown, Unknown,
Core, Core,
Atom, Atom,
Nehalem Nehalem,
SandyBridge
} }
private readonly Sensor[] coreTemperatures; private readonly Sensor[] coreTemperatures;
@@ -68,6 +69,20 @@ namespace OpenHardwareMonitor.Hardware.CPU {
return result; return result;
} }
private float[] GetTjMaxFromMSR() {
uint eax, edx;
float[] result = new float[coreCount];
for (int i = 0; i < coreCount; i++) {
if (Ring0.RdmsrTx(IA32_TEMPERATURE_TARGET, out eax,
out edx, 1UL << cpuid[i][0].Thread)) {
result[i] = (eax >> 16) & 0xFF;
} else {
result[i] = 100;
}
}
return result;
}
public IntelCPU(int processorIndex, CPUID[][] cpuid, ISettings settings) public IntelCPU(int processorIndex, CPUID[][] cpuid, ISettings settings)
: base(processorIndex, cpuid, settings) : base(processorIndex, cpuid, settings)
{ {
@@ -111,19 +126,17 @@ namespace OpenHardwareMonitor.Hardware.CPU {
} break; } break;
case 0x1A: // Intel Core i7 LGA1366 (45nm) case 0x1A: // Intel Core i7 LGA1366 (45nm)
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm) case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
case 0x1F: // Intel Core i5, i7
case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm) case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core
case 0x2E: // Intel Xeon Processor 7500 series
microarchitecture = Microarchitecture.Nehalem; microarchitecture = Microarchitecture.Nehalem;
uint eax, edx; tjMax = GetTjMaxFromMSR();
tjMax = new float[coreCount]; break;
for (int i = 0; i < coreCount; i++) { case 0x2A: // Intel Core i5, i7 2xxx LGA1155 (32nm)
if (Ring0.RdmsrTx(IA32_TEMPERATURE_TARGET, out eax, case 0x2D: // Next Generation Intel Xeon Processor
out edx, 1UL << cpuid[i][0].Thread)) { microarchitecture = Microarchitecture.SandyBridge;
tjMax[i] = (eax >> 16) & 0xFF; tjMax = GetTjMaxFromMSR();
} else {
tjMax[i] = 100;
}
}
break; break;
default: default:
microarchitecture = Microarchitecture.Unknown; microarchitecture = Microarchitecture.Unknown;
@@ -147,7 +160,8 @@ namespace OpenHardwareMonitor.Hardware.CPU {
((edx >> 8) & 0x1f) + 0.5 * ((edx >> 14) & 1); ((edx >> 8) & 0x1f) + 0.5 * ((edx >> 14) & 1);
} }
} break; } break;
case Microarchitecture.Nehalem: { case Microarchitecture.Nehalem:
case Microarchitecture.SandyBridge: {
uint eax, edx; uint eax, edx;
if (Ring0.Rdmsr(MSR_PLATFORM_INFO, out eax, out edx)) { if (Ring0.Rdmsr(MSR_PLATFORM_INFO, out eax, out edx)) {
timeStampCounterMultiplier = (eax >> 8) & 0xff; timeStampCounterMultiplier = (eax >> 8) & 0xff;
@@ -241,7 +255,9 @@ namespace OpenHardwareMonitor.Hardware.CPU {
{ {
newBusClock = newBusClock =
TimeStampCounterFrequency / timeStampCounterMultiplier; TimeStampCounterFrequency / timeStampCounterMultiplier;
if (microarchitecture == Microarchitecture.Nehalem) { if (microarchitecture == Microarchitecture.Nehalem ||
microarchitecture == Microarchitecture.SandyBridge)
{
uint multiplier = eax & 0xff; uint multiplier = eax & 0xff;
coreClocks[i].Value = (float)(multiplier * newBusClock); coreClocks[i].Value = (float)(multiplier * newBusClock);
} else { } else {