mirror of
https://github.com/openhardwaremonitor/openhardwaremonitor
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286 lines
10 KiB
C#
286 lines
10 KiB
C#
/*
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Version: MPL 1.1/GPL 2.0/LGPL 2.1
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The contents of this file are subject to the Mozilla Public License Version
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1.1 (the "License"); you may not use this file except in compliance with
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the License. You may obtain a copy of the License at
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http://www.mozilla.org/MPL/
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Software distributed under the License is distributed on an "AS IS" basis,
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WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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for the specific language governing rights and limitations under the License.
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The Original Code is the Open Hardware Monitor code.
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The Initial Developer of the Original Code is
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Michael Möller <m.moeller@gmx.ch>.
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Portions created by the Initial Developer are Copyright (C) 2009-2010
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the Initial Developer. All Rights Reserved.
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Contributor(s):
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Alternatively, the contents of this file may be used under the terms of
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either the GNU General Public License Version 2 or later (the "GPL"), or
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the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
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in which case the provisions of the GPL or the LGPL are applicable instead
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of those above. If you wish to allow use of your version of this file only
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under the terms of either the GPL or the LGPL, and not to allow others to
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use your version of this file under the terms of the MPL, indicate your
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decision by deleting the provisions above and replace them with the notice
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and other provisions required by the GPL or the LGPL. If you do not delete
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the provisions above, a recipient may use your version of this file under
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the terms of any one of the MPL, the GPL or the LGPL.
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*/
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using System;
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using System.Globalization;
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using System.Text;
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namespace OpenHardwareMonitor.Hardware.CPU {
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internal sealed class IntelCPU : GenericCPU {
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private enum Microarchitecture {
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Unknown,
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Core,
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Atom,
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Nehalem,
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SandyBridge
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}
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private readonly Sensor[] coreTemperatures;
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private readonly Sensor[] coreClocks;
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private readonly Sensor busClock;
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private readonly Microarchitecture microarchitecture;
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private readonly double timeStampCounterMultiplier;
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private const uint IA32_THERM_STATUS_MSR = 0x019C;
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private const uint IA32_TEMPERATURE_TARGET = 0x01A2;
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private const uint IA32_PERF_STATUS = 0x0198;
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private const uint MSR_PLATFORM_INFO = 0xCE;
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private float[] Floats(float f) {
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float[] result = new float[coreCount];
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for (int i = 0; i < coreCount; i++)
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result[i] = f;
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return result;
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}
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private float[] GetTjMaxFromMSR() {
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uint eax, edx;
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float[] result = new float[coreCount];
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for (int i = 0; i < coreCount; i++) {
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if (Ring0.RdmsrTx(IA32_TEMPERATURE_TARGET, out eax,
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out edx, 1UL << cpuid[i][0].Thread)) {
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result[i] = (eax >> 16) & 0xFF;
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} else {
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result[i] = 100;
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}
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}
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return result;
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}
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public IntelCPU(int processorIndex, CPUID[][] cpuid, ISettings settings)
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: base(processorIndex, cpuid, settings)
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{
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// set tjMax
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float[] tjMax;
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switch (family) {
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case 0x06: {
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switch (model) {
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case 0x0F: // Intel Core 2 (65nm)
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microarchitecture = Microarchitecture.Core;
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switch (stepping) {
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case 0x06: // B2
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switch (coreCount) {
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case 2:
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tjMax = Floats(80 + 10); break;
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case 4:
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tjMax = Floats(90 + 10); break;
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default:
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tjMax = Floats(85 + 10); break;
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}
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tjMax = Floats(80 + 10); break;
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case 0x0B: // G0
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tjMax = Floats(90 + 10); break;
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case 0x0D: // M0
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tjMax = Floats(85 + 10); break;
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default:
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tjMax = Floats(85 + 10); break;
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} break;
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case 0x17: // Intel Core 2 (45nm)
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microarchitecture = Microarchitecture.Core;
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tjMax = Floats(100); break;
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case 0x1C: // Intel Atom (45nm)
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microarchitecture = Microarchitecture.Atom;
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switch (stepping) {
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case 0x02: // C0
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tjMax = Floats(90); break;
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case 0x0A: // A0, B0
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tjMax = Floats(100); break;
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default:
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tjMax = Floats(90); break;
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} break;
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case 0x1A: // Intel Core i7 LGA1366 (45nm)
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case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
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case 0x1F: // Intel Core i5, i7
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case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
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case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core
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case 0x2E: // Intel Xeon Processor 7500 series
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microarchitecture = Microarchitecture.Nehalem;
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tjMax = GetTjMaxFromMSR();
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break;
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case 0x2A: // Intel Core i5, i7 2xxx LGA1155 (32nm)
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case 0x2D: // Next Generation Intel Xeon Processor
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microarchitecture = Microarchitecture.SandyBridge;
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tjMax = GetTjMaxFromMSR();
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break;
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default:
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microarchitecture = Microarchitecture.Unknown;
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tjMax = Floats(100);
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break;
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}
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} break;
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default:
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microarchitecture = Microarchitecture.Unknown;
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tjMax = Floats(100);
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break;
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}
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// set timeStampCounterMultiplier
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switch (microarchitecture) {
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case Microarchitecture.Atom:
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case Microarchitecture.Core: {
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uint eax, edx;
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if (Ring0.Rdmsr(IA32_PERF_STATUS, out eax, out edx)) {
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timeStampCounterMultiplier =
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((edx >> 8) & 0x1f) + 0.5 * ((edx >> 14) & 1);
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}
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} break;
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case Microarchitecture.Nehalem:
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case Microarchitecture.SandyBridge: {
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uint eax, edx;
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if (Ring0.Rdmsr(MSR_PLATFORM_INFO, out eax, out edx)) {
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timeStampCounterMultiplier = (eax >> 8) & 0xff;
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}
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} break;
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default:
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timeStampCounterMultiplier = 1;
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break;
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}
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// check if processor supports a digital thermal sensor
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if (cpuid[0][0].Data.GetLength(0) > 6 &&
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(cpuid[0][0].Data[6, 0] & 1) != 0) {
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coreTemperatures = new Sensor[coreCount];
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for (int i = 0; i < coreTemperatures.Length; i++) {
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coreTemperatures[i] = new Sensor(CoreString(i), i,
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SensorType.Temperature, this, new [] {
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new ParameterDescription(
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"TjMax [°C]", "TjMax temperature of the core.\n" +
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"Temperature = TjMax - TSlope * Value.", tjMax[i]),
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new ParameterDescription("TSlope [°C]",
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"Temperature slope of the digital thermal sensor.\n" +
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"Temperature = TjMax - TSlope * Value.", 1)}, settings);
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ActivateSensor(coreTemperatures[i]);
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}
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} else {
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coreTemperatures = new Sensor[0];
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}
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busClock = new Sensor("Bus Speed", 0, SensorType.Clock, this, settings);
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coreClocks = new Sensor[coreCount];
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for (int i = 0; i < coreClocks.Length; i++) {
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coreClocks[i] =
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new Sensor(CoreString(i), i + 1, SensorType.Clock, this, settings);
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if (HasTimeStampCounter)
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ActivateSensor(coreClocks[i]);
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}
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Update();
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}
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protected override uint[] GetMSRs() {
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return new [] {
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MSR_PLATFORM_INFO,
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IA32_PERF_STATUS ,
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IA32_THERM_STATUS_MSR,
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IA32_TEMPERATURE_TARGET
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};
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}
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public override string GetReport() {
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StringBuilder r = new StringBuilder();
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r.Append(base.GetReport());
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r.Append("Time Stamp Counter Multiplier: ");
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r.AppendLine(timeStampCounterMultiplier.ToString(
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CultureInfo.InvariantCulture));
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r.AppendLine();
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return r.ToString();
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}
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public override void Update() {
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base.Update();
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for (int i = 0; i < coreTemperatures.Length; i++) {
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uint eax, edx;
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if (Ring0.RdmsrTx(
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IA32_THERM_STATUS_MSR, out eax, out edx,
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1UL << cpuid[i][0].Thread)) {
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// if reading is valid
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if ((eax & 0x80000000) != 0) {
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// get the dist from tjMax from bits 22:16
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float deltaT = ((eax & 0x007F0000) >> 16);
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float tjMax = coreTemperatures[i].Parameters[0].Value;
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float tSlope = coreTemperatures[i].Parameters[1].Value;
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coreTemperatures[i].Value = tjMax - tSlope * deltaT;
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} else {
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coreTemperatures[i].Value = null;
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}
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}
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}
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if (HasTimeStampCounter) {
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double newBusClock = 0;
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uint eax, edx;
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for (int i = 0; i < coreClocks.Length; i++) {
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System.Threading.Thread.Sleep(1);
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if (Ring0.RdmsrTx(IA32_PERF_STATUS, out eax, out edx,
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1UL << cpuid[i][0].Thread))
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{
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newBusClock =
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TimeStampCounterFrequency / timeStampCounterMultiplier;
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switch (microarchitecture) {
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case Microarchitecture.Nehalem: {
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uint multiplier = eax & 0xff;
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coreClocks[i].Value = (float)(multiplier * newBusClock);
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} break;
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case Microarchitecture.SandyBridge: {
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uint multiplier = (eax >> 8) & 0xff;
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coreClocks[i].Value = (float)(multiplier * newBusClock);
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} break;
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default: {
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double multiplier =
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((eax >> 8) & 0x1f) + 0.5 * ((eax >> 14) & 1);
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coreClocks[i].Value = (float)(multiplier * newBusClock);
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} break;
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}
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} else {
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// if IA32_PERF_STATUS is not available, assume TSC frequency
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coreClocks[i].Value = (float)TimeStampCounterFrequency;
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}
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}
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if (newBusClock > 0) {
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this.busClock.Value = (float)newBusClock;
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ActivateSensor(this.busClock);
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}
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}
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}
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}
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}
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