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Increase number of registers to 16.
With eight 32-bit registers, we can only store two IPv6 addresses, which is pretty tight. Signed-off-by: Justin Pettit <jpettit@ovn.org> Acked-by: Ben Pfaff <blp@ovn.org>
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@@ -23,10 +23,10 @@
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/* This sequence number should be incremented whenever anything involving flows
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* or the wildcarding of flows changes. This will cause build assertion
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* failures in places which likely need to be updated. */
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#define FLOW_WC_SEQ 35
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#define FLOW_WC_SEQ 36
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/* Number of Open vSwitch extension 32-bit registers. */
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#define FLOW_N_REGS 8
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#define FLOW_N_REGS 16
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BUILD_ASSERT_DECL(FLOW_N_REGS <= NXM_NX_MAX_REGS);
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BUILD_ASSERT_DECL(FLOW_N_REGS % 2 == 0); /* Even. */
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@@ -129,8 +129,8 @@ BUILD_ASSERT_DECL(sizeof(struct flow_tnl) % sizeof(uint64_t) == 0);
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/* Remember to update FLOW_WC_SEQ when changing 'struct flow'. */
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BUILD_ASSERT_DECL(offsetof(struct flow, igmp_group_ip4) + sizeof(uint32_t)
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== sizeof(struct flow_tnl) + 216
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&& FLOW_WC_SEQ == 35);
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== sizeof(struct flow_tnl) + 248
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&& FLOW_WC_SEQ == 36);
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/* Incremental points at which flow classification may be performed in
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* segments.
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