mirror of
https://github.com/openvswitch/ovs
synced 2025-09-01 06:45:17 +00:00
nicira-ext: Increase the number of NXM registers to 8.
Requested-by: Amar Padmanabhan <amar@nicira.com> Signed-off-by: Ethan Jackson <ethan@nicira.com>
This commit is contained in:
Ethan Jackson
1
NEWS
1
NEWS
@@ -2,6 +2,7 @@ post-v1.6.0
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------------------------
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- kernel modules are renamed. openvswitch_mod.ko is now
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openvswitch.ko and brcompat_mod.ko is now brcompat.ko.
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- Increased the number of NXM registers to 8.
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v1.6.0 - xx xxx xxxx
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@@ -1565,6 +1565,12 @@ OFP_ASSERT(sizeof(struct nx_action_output_reg) == 24);
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#define NXM_NX_REG3_W NXM_HEADER_W(0x0001, 3, 4)
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#define NXM_NX_REG4 NXM_HEADER (0x0001, 4, 4)
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#define NXM_NX_REG4_W NXM_HEADER_W(0x0001, 4, 4)
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#define NXM_NX_REG5 NXM_HEADER (0x0001, 5, 4)
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#define NXM_NX_REG5_W NXM_HEADER_W(0x0001, 5, 4)
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#define NXM_NX_REG6 NXM_HEADER (0x0001, 6, 4)
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#define NXM_NX_REG6_W NXM_HEADER_W(0x0001, 6, 4)
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#define NXM_NX_REG7 NXM_HEADER (0x0001, 7, 4)
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#define NXM_NX_REG7_W NXM_HEADER_W(0x0001, 7, 4)
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/* Tunnel ID.
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*
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@@ -491,7 +491,7 @@ cls_rule_format(const struct cls_rule *rule, struct ds *s)
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int i;
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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if (rule->priority != OFP_DEFAULT_PRIORITY) {
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ds_put_format(s, "priority=%d,", rule->priority);
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@@ -1164,7 +1164,7 @@ flow_equal_except(const struct flow *a, const struct flow *b,
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const flow_wildcards_t wc = wildcards->wildcards;
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int i;
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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for (i = 0; i < FLOW_N_REGS; i++) {
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if ((a->regs[i] ^ b->regs[i]) & wildcards->reg_masks[i]) {
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20
lib/flow.c
20
lib/flow.c
@@ -444,7 +444,7 @@ flow_zero_wildcards(struct flow *flow, const struct flow_wildcards *wildcards)
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const flow_wildcards_t wc = wildcards->wildcards;
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int i;
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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for (i = 0; i < FLOW_N_REGS; i++) {
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flow->regs[i] &= wildcards->reg_masks[i];
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@@ -507,6 +507,8 @@ flow_zero_wildcards(struct flow *flow, const struct flow_wildcards *wildcards)
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void
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flow_get_metadata(const struct flow *flow, struct flow_metadata *fmd)
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{
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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fmd->tun_id = flow->tun_id;
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fmd->tun_id_mask = htonll(UINT64_MAX);
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@@ -594,7 +596,7 @@ flow_print(FILE *stream, const struct flow *flow)
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void
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flow_wildcards_init_catchall(struct flow_wildcards *wc)
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{
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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wc->wildcards = FWW_ALL;
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wc->tun_id_mask = htonll(0);
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@@ -615,7 +617,7 @@ flow_wildcards_init_catchall(struct flow_wildcards *wc)
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void
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flow_wildcards_init_exact(struct flow_wildcards *wc)
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{
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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wc->wildcards = 0;
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wc->tun_id_mask = htonll(UINT64_MAX);
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@@ -638,7 +640,7 @@ flow_wildcards_is_exact(const struct flow_wildcards *wc)
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{
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int i;
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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if (wc->wildcards
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|| wc->tun_id_mask != htonll(UINT64_MAX)
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@@ -669,7 +671,7 @@ flow_wildcards_is_catchall(const struct flow_wildcards *wc)
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{
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int i;
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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if (wc->wildcards != FWW_ALL
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|| wc->tun_id_mask != htonll(0)
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@@ -703,7 +705,7 @@ flow_wildcards_combine(struct flow_wildcards *dst,
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{
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int i;
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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dst->wildcards = src1->wildcards | src2->wildcards;
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dst->tun_id_mask = src1->tun_id_mask & src2->tun_id_mask;
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@@ -728,7 +730,7 @@ flow_wildcards_hash(const struct flow_wildcards *wc, uint32_t basis)
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/* If you change struct flow_wildcards and thereby trigger this
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* assertion, please check that the new struct flow_wildcards has no holes
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* in it before you update the assertion. */
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BUILD_ASSERT_DECL(sizeof *wc == 60 + FLOW_N_REGS * 4);
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BUILD_ASSERT_DECL(sizeof *wc == 64 + FLOW_N_REGS * 4);
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return hash_bytes(wc, sizeof *wc, basis);
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}
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@@ -740,7 +742,7 @@ flow_wildcards_equal(const struct flow_wildcards *a,
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{
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int i;
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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if (a->wildcards != b->wildcards
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|| a->tun_id_mask != b->tun_id_mask
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@@ -772,7 +774,7 @@ flow_wildcards_has_extra(const struct flow_wildcards *a,
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int i;
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struct in6_addr ipv6_masked;
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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for (i = 0; i < FLOW_N_REGS; i++) {
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if ((a->reg_masks[i] & b->reg_masks[i]) != b->reg_masks[i]) {
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16
lib/flow.h
16
lib/flow.h
@@ -35,9 +35,9 @@ struct ofpbuf;
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/* This sequence number should be incremented whenever anything involving flows
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* or the wildcarding of flows changes. This will cause build assertion
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* failures in places which likely need to be updated. */
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#define FLOW_WC_SEQ 8
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#define FLOW_WC_SEQ 9
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#define FLOW_N_REGS 5
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#define FLOW_N_REGS 8
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BUILD_ASSERT_DECL(FLOW_N_REGS <= NXM_NX_MAX_REGS);
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/* Used for struct flow's dl_type member for frames that have no Ethernet
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@@ -75,7 +75,7 @@ struct flow {
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uint8_t arp_tha[6]; /* ARP/ND target hardware address. */
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uint8_t nw_ttl; /* IP TTL/Hop Limit. */
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uint8_t nw_frag; /* FLOW_FRAG_* flags. */
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uint8_t reserved[6]; /* Reserved for 64-bit packing. */
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uint8_t reserved[2]; /* Reserved for 64-bit packing. */
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};
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/* Represents the metadata fields of struct flow. The masks are used to
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@@ -94,13 +94,13 @@ struct flow_metadata {
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/* Assert that there are FLOW_SIG_SIZE bytes of significant data in "struct
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* flow", followed by FLOW_PAD_SIZE bytes of padding. */
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#define FLOW_SIG_SIZE (110 + FLOW_N_REGS * 4)
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#define FLOW_PAD_SIZE 6
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#define FLOW_PAD_SIZE 2
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BUILD_ASSERT_DECL(offsetof(struct flow, nw_frag) == FLOW_SIG_SIZE - 1);
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BUILD_ASSERT_DECL(sizeof(((struct flow *)0)->nw_frag) == 1);
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BUILD_ASSERT_DECL(sizeof(struct flow) == FLOW_SIG_SIZE + FLOW_PAD_SIZE);
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/* Remember to update FLOW_WC_SEQ when changing 'struct flow'. */
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BUILD_ASSERT_DECL(FLOW_SIG_SIZE == 130 && FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_SIG_SIZE == 142 && FLOW_WC_SEQ == 9);
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void flow_extract(struct ofpbuf *, uint32_t priority, ovs_be64 tun_id,
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uint16_t in_port, struct flow *);
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@@ -165,7 +165,7 @@ typedef unsigned int OVS_BITWISE flow_wildcards_t;
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#define FWW_ALL ((OVS_FORCE flow_wildcards_t) (((1 << 13)) - 1))
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/* Remember to update FLOW_WC_SEQ when adding or removing FWW_*. */
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BUILD_ASSERT_DECL(FWW_ALL == ((1 << 13) - 1) && FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FWW_ALL == ((1 << 13) - 1) && FLOW_WC_SEQ == 9);
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/* Information on wildcards for a flow, as a supplement to "struct flow".
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*
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@@ -183,11 +183,11 @@ struct flow_wildcards {
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ovs_be16 tp_src_mask; /* 1-bit in each significant tp_src bit. */
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ovs_be16 tp_dst_mask; /* 1-bit in each significant tp_dst bit. */
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uint8_t nw_frag_mask; /* 1-bit in each significant nw_frag bit. */
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uint8_t zeros[1]; /* Padding field set to zero. */
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uint8_t zeros[5]; /* Padding field set to zero. */
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};
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/* Remember to update FLOW_WC_SEQ when updating struct flow_wildcards. */
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BUILD_ASSERT_DECL(sizeof(struct flow_wildcards) == 80 && FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(sizeof(struct flow_wildcards) == 96 && FLOW_WC_SEQ == 9);
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void flow_wildcards_init_catchall(struct flow_wildcards *);
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void flow_wildcards_init_exact(struct flow_wildcards *);
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@@ -91,6 +91,15 @@ static const struct mf_field mf_fields[MFF_N_IDS] = {
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REGISTER(4),
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#endif
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#if FLOW_N_REGS > 5
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REGISTER(5),
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#endif
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#if FLOW_N_REGS > 6
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REGISTER(6),
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#endif
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#if FLOW_N_REGS > 7
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REGISTER(7),
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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@@ -534,6 +543,15 @@ mf_is_all_wild(const struct mf_field *mf, const struct flow_wildcards *wc)
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case MFF_REG4:
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#endif
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#if FLOW_N_REGS > 5
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case MFF_REG5:
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#endif
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#if FLOW_N_REGS > 6
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case MFF_REG6:
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#endif
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#if FLOW_N_REGS > 7
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case MFF_REG7:
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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return !wc->reg_masks[mf->id - MFF_REG0];
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@@ -633,6 +651,15 @@ mf_get_mask(const struct mf_field *mf, const struct flow_wildcards *wc,
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case MFF_REG4:
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#endif
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#if FLOW_N_REGS > 5
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case MFF_REG5:
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#endif
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#if FLOW_N_REGS > 6
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case MFF_REG6:
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#endif
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#if FLOW_N_REGS > 7
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case MFF_REG7:
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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mask->be32 = htonl(wc->reg_masks[mf->id - MFF_REG0]);
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@@ -824,6 +851,15 @@ mf_is_value_valid(const struct mf_field *mf, const union mf_value *value)
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case MFF_REG4:
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#endif
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#if FLOW_N_REGS > 5
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case MFF_REG5:
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#endif
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#if FLOW_N_REGS > 6
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case MFF_REG6:
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#endif
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#if FLOW_N_REGS > 7
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case MFF_REG7:
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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case MFF_ETH_SRC:
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@@ -909,6 +945,15 @@ mf_get_value(const struct mf_field *mf, const struct flow *flow,
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case MFF_REG4:
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#endif
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#if FLOW_N_REGS > 5
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case MFF_REG5:
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#endif
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#if FLOW_N_REGS > 6
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case MFF_REG6:
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#endif
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#if FLOW_N_REGS > 7
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case MFF_REG7:
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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value->be32 = htonl(flow->regs[mf->id - MFF_REG0]);
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@@ -1068,6 +1113,15 @@ mf_set_value(const struct mf_field *mf,
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case MFF_REG4:
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#endif
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#if FLOW_N_REGS > 5
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case MFF_REG5:
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#endif
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#if FLOW_N_REGS > 6
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case MFF_REG6:
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#endif
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#if FLOW_N_REGS > 7
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case MFF_REG7:
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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#if FLOW_N_REGS > 0
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@@ -1229,6 +1283,15 @@ mf_set_flow_value(const struct mf_field *mf,
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case MFF_REG4:
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#endif
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#if FLOW_N_REGS > 5
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case MFF_REG5:
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#endif
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#if FLOW_N_REGS > 6
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case MFF_REG6:
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#endif
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#if FLOW_N_REGS > 7
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case MFF_REG7:
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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#if FLOW_N_REGS > 0
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@@ -1397,6 +1460,21 @@ mf_set_wild(const struct mf_field *mf, struct cls_rule *rule)
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break;
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#endif
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#if FLOW_N_REGS > 5
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case MFF_REG5:
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cls_rule_set_reg_masked(rule, 5, 0, 0);
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break;
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#endif
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#if FLOW_N_REGS > 6
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case MFF_REG6:
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cls_rule_set_reg_masked(rule, 6, 0, 0);
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break;
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#endif
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#if FLOW_N_REGS > 7
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case MFF_REG7:
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cls_rule_set_reg_masked(rule, 7, 0, 0);
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break;
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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@@ -1588,6 +1666,15 @@ mf_set(const struct mf_field *mf,
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case MFF_REG4:
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#endif
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#if FLOW_N_REGS > 5
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case MFF_REG5:
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#endif
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#if FLOW_N_REGS > 6
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case MFF_REG6:
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#endif
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#if FLOW_N_REGS > 7
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case MFF_REG7:
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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cls_rule_set_reg_masked(rule, mf->id - MFF_REG0,
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@@ -1732,6 +1819,15 @@ mf_random_value(const struct mf_field *mf, union mf_value *value)
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case MFF_REG4:
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#endif
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#if FLOW_N_REGS > 5
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case MFF_REG5:
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#endif
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#if FLOW_N_REGS > 6
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case MFF_REG6:
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#endif
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#if FLOW_N_REGS > 7
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case MFF_REG7:
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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case MFF_ETH_SRC:
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@@ -50,6 +50,15 @@ enum mf_field_id {
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MFF_REG4, /* be32 */
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#endif
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#if FLOW_N_REGS > 5
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MFF_REG5, /* be32 */
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#endif
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#if FLOW_N_REGS > 6
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MFF_REG6, /* be32 */
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#endif
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#if FLOW_N_REGS > 7
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MFF_REG7, /* be32 */
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#endif
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#if FLOW_N_REGS > 8
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#error
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#endif
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@@ -471,7 +471,7 @@ nx_put_match(struct ofpbuf *b, const struct cls_rule *cr,
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int match_len;
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int i;
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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/* Metadata. */
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if (!(wc & FWW_IN_PORT)) {
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@@ -20,6 +20,7 @@
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#include <stdint.h>
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#include <sys/types.h>
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#include <netinet/in.h>
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#include "flow.h"
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#include "openvswitch/types.h"
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#include "ofp-errors.h"
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@@ -89,6 +90,7 @@ void nxm_decode(struct mf_subfield *, ovs_be32 header, ovs_be16 ofs_nbits);
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void nxm_decode_discrete(struct mf_subfield *, ovs_be32 header,
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ovs_be16 ofs, ovs_be16 n_bits);
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BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
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/* Upper bound on the length of an nx_match. The longest nx_match (an
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* IPV6 neighbor discovery message using 5 registers) would be:
|
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*
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@@ -116,9 +118,12 @@ void nxm_decode_discrete(struct mf_subfield *, ovs_be32 header,
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* NXM_NX_REG_W(2) 4 4 4 12
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* NXM_NX_REG_W(3) 4 4 4 12
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* NXM_NX_REG_W(4) 4 4 4 12
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* NXM_NX_REG_W(5) 4 4 4 12
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* NXM_NX_REG_W(6) 4 4 4 12
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* NXM_NX_REG_W(7) 4 4 4 12
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* NXM_NX_TUN_ID_W 4 8 8 20
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||||
* -------------------------------------------
|
||||
* total 275
|
||||
* total 311
|
||||
*
|
||||
* So this value is conservative.
|
||||
*/
|
||||
|
||||
@@ -101,7 +101,7 @@ static const flow_wildcards_t WC_INVARIANTS = 0
|
||||
void
|
||||
ofputil_wildcard_from_openflow(uint32_t ofpfw, struct flow_wildcards *wc)
|
||||
{
|
||||
BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
|
||||
BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
|
||||
|
||||
/* Initialize most of rule->wc. */
|
||||
flow_wildcards_init_catchall(wc);
|
||||
@@ -1166,7 +1166,7 @@ ofputil_usable_protocols(const struct cls_rule *rule)
|
||||
{
|
||||
const struct flow_wildcards *wc = &rule->wc;
|
||||
|
||||
BUILD_ASSERT_DECL(FLOW_WC_SEQ == 8);
|
||||
BUILD_ASSERT_DECL(FLOW_WC_SEQ == 9);
|
||||
|
||||
/* Only NXM supports separately wildcards the Ethernet multicast bit. */
|
||||
if (!(wc->wildcards & FWW_DL_DST) != !(wc->wildcards & FWW_ETH_MCAST)) {
|
||||
|
||||
@@ -23,7 +23,9 @@ OVS_VSWITCHD_START
|
||||
AT_DATA([flows.txt], [dnl
|
||||
in_port=90 actions=resubmit:2,resubmit:3,resubmit:4,resubmit:91
|
||||
in_port=91 actions=resubmit:5,resubmit:6,resubmit:7,resubmit:92
|
||||
in_port=92 actions=resubmit:8,resubmit:9,resubmit:10,resubmit:11
|
||||
in_port=92 actions=resubmit:8,resubmit:9,resubmit:10,resubmit:11,resubmit:93
|
||||
in_port=93 actions=resubmit:12,resubmit:13,resubmit:14,resubmit:15
|
||||
|
||||
in_port=2 actions=load:0x000db000->NXM_NX_REG0[[]]
|
||||
in_port=3 actions=load:0xdea->NXM_NX_REG0[[20..31]]
|
||||
in_port=4 actions=load:0xeef->NXM_NX_REG0[[0..11]]
|
||||
@@ -34,11 +36,17 @@ in_port=8 actions=move:NXM_NX_REG1[[0..11]]->NXM_NX_REG2[[20..3
|
||||
in_port=9,reg0=0xdeadbeef actions=output:20
|
||||
in_port=10,reg1=0xdeadbeef actions=output:21
|
||||
in_port=11,reg2=0xeef22dea actions=output:22
|
||||
|
||||
dnl Sanilty check all registers
|
||||
in_port=12 actions=load:0x10->NXM_NX_REG0[[]],load:0x11->NXM_NX_REG1[[]],load:0x12->NXM_NX_REG2[[]]
|
||||
in_port=13 actions=load:0x13->NXM_NX_REG3[[]],load:0x14->NXM_NX_REG4[[]],load:0x15->NXM_NX_REG5[[]]
|
||||
in_port=14 actions=load:0x16->NXM_NX_REG6[[]],load:0x17->NXM_NX_REG7[[]]
|
||||
in_port=15,reg0=0x10,reg1=0x11,reg2=0x12,reg3=0x13,reg4=0x14,reg5=0x15,reg6=0x16,reg7=0x17 actions=output:33
|
||||
])
|
||||
AT_CHECK([ovs-ofctl add-flows br0 flows.txt])
|
||||
AT_CHECK([ovs-appctl ofproto/trace br0 'in_port(90),eth(src=50:54:00:00:00:05,dst=50:54:00:00:00:07),eth_type(0x0800),ipv4(src=192.168.0.1,dst=192.168.0.2,proto=1,tos=0,ttl=128,frag=no),icmp(type=8,code=0)'], [0], [stdout])
|
||||
AT_CHECK([tail -1 stdout], [0],
|
||||
[Datapath actions: 20,21,22
|
||||
[Datapath actions: 20,21,22,33
|
||||
])
|
||||
OVS_VSWITCHD_STOP
|
||||
AT_CLEANUP
|
||||
@@ -87,7 +95,7 @@ AT_CHECK([ovs-ofctl monitor br0 65534 invalid_ttl --detach --pidfile 2> ofctl_mo
|
||||
AT_CHECK([ovs-appctl ofproto/trace br0 'in_port(1),eth(src=50:54:00:00:00:05,dst=50:54:00:00:00:07),eth_type(0x0800),ipv4(src=192.168.0.1,dst=192.168.0.2,proto=1,tos=0,ttl=2,frag=no)' -generate], [0], [stdout])
|
||||
OVS_WAIT_UNTIL([ovs-appctl -t ovs-ofctl exit])
|
||||
AT_CHECK([cat ofctl_monitor.log], [0], [dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=1 total_len=42 in_port=1 tun_id=0x0 reg0=0x0 reg1=0x0 reg2=0x0 reg3=0x0 reg4=0x0 (via invalid_ttl) data_len=42 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=1 total_len=42 in_port=1 tun_id=0x0 reg0=0x0 reg1=0x0 reg2=0x0 reg3=0x0 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via invalid_ttl) data_len=42 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(0) mac(50:54:00:00:00:05->50:54:00:00:00:07) type:0800 proto:1 tos:0 ttl:1 ip(192.168.0.1->192.168.0.2)
|
||||
])
|
||||
OVS_VSWITCHD_STOP
|
||||
@@ -309,31 +317,31 @@ done
|
||||
|
||||
OVS_WAIT_UNTIL([ovs-appctl -t ovs-ofctl exit])
|
||||
AT_CHECK([cat ofctl_monitor.log], [0], [dnl
|
||||
NXT_PACKET_IN (xid=0x0): cookie=0x1 total_len=60 in_port=1 tun_id=0x0 reg0=0x0 reg1=0x0 reg2=0x0 reg3=0x0 reg4=0x0 (via action) data_len=60 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): cookie=0x1 total_len=60 in_port=1 tun_id=0x0 reg0=0x0 reg1=0x0 reg2=0x0 reg3=0x0 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=60 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(0) mac(20:22:22:22:22:22->50:54:00:00:00:07) type:0800 proto:6 tos:0 ttl:0 ip(192.168.0.1->192.168.0.2) port(8->11) tcp_csum:0
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=1 cookie=0x3 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x0 reg2=0x0 reg3=0x0 reg4=0x0 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=1 cookie=0x3 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x0 reg2=0x0 reg3=0x0 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(20:22:22:22:22:22->50:54:00:00:00:07) type:0800 proto:6 tos:0 ttl:0 ip(192.168.0.1->192.168.0.2) port(8->11) tcp_csum:0
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=2 cookie=0x4 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x0 reg3=0x0 reg4=0x0 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=2 cookie=0x4 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x0 reg3=0x0 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->50:54:00:00:00:07) type:0800 proto:6 tos:0 ttl:0 ip(192.168.0.1->192.168.0.2) port(8->11) tcp_csum:0
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=3 cookie=0x5 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x0 reg4=0x0 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=3 cookie=0x5 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x0 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:6 tos:0 ttl:0 ip(192.168.0.1->192.168.0.2) port(8->11) tcp_csum:0
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=4 cookie=0x6 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x0 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=4 cookie=0x6 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:6 tos:0 ttl:0 ip(83.83.83.83->192.168.0.2) port(8->11) tcp_csum:1a03
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=5 cookie=0x7 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=5 cookie=0x7 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:6 tos:0 ttl:0 ip(83.83.83.83->84.84.84.84) port(8->11) tcp_csum:3205
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=6 cookie=0x8 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=6 cookie=0x8 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:6 tos:0 ttl:0 ip(83.83.83.83->84.84.84.84) port(85->11) tcp_csum:31b8
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=7 cookie=0x9 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=7 cookie=0x9 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:6 tos:0 ttl:0 ip(83.83.83.83->84.84.84.84) port(85->86) tcp_csum:316d
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=7 cookie=0x9 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=7 cookie=0x9 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:6 tos:0 ttl:0 ip(83.83.83.83->84.84.84.84) port(85->86) tcp_csum:316d
|
||||
])
|
||||
|
||||
@@ -346,31 +354,31 @@ done
|
||||
|
||||
OVS_WAIT_UNTIL([ovs-appctl -t ovs-ofctl exit])
|
||||
AT_CHECK([cat ofctl_monitor.log], [0], [dnl
|
||||
NXT_PACKET_IN (xid=0x0): cookie=0x1 total_len=60 in_port=1 tun_id=0x0 reg0=0x0 reg1=0x0 reg2=0x0 reg3=0x0 reg4=0x0 (via action) data_len=60 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): cookie=0x1 total_len=60 in_port=1 tun_id=0x0 reg0=0x0 reg1=0x0 reg2=0x0 reg3=0x0 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=60 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(0) mac(20:22:22:22:22:22->50:54:00:00:00:07) type:0800 proto:17 tos:0 ttl:0 ip(192.168.0.1->192.168.0.2) port(8->11) udp_csum:1234
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=1 cookie=0x3 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x0 reg2=0x0 reg3=0x0 reg4=0x0 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=1 cookie=0x3 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x0 reg2=0x0 reg3=0x0 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(20:22:22:22:22:22->50:54:00:00:00:07) type:0800 proto:17 tos:0 ttl:0 ip(192.168.0.1->192.168.0.2) port(8->11) udp_csum:1234
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=2 cookie=0x4 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x0 reg3=0x0 reg4=0x0 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=2 cookie=0x4 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x0 reg3=0x0 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->50:54:00:00:00:07) type:0800 proto:17 tos:0 ttl:0 ip(192.168.0.1->192.168.0.2) port(8->11) udp_csum:1234
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=3 cookie=0x5 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x0 reg4=0x0 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=3 cookie=0x5 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x0 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:17 tos:0 ttl:0 ip(192.168.0.1->192.168.0.2) port(8->11) udp_csum:1234
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=4 cookie=0x6 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x0 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=4 cookie=0x6 total_len=64 in_port=1 tun_id=0x0 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x0 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:17 tos:0 ttl:0 ip(83.83.83.83->192.168.0.2) port(8->11) udp_csum:2c37
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=5 cookie=0x7 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=5 cookie=0x7 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:17 tos:0 ttl:0 ip(83.83.83.83->84.84.84.84) port(8->11) udp_csum:4439
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=6 cookie=0x8 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=6 cookie=0x8 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:17 tos:0 ttl:0 ip(83.83.83.83->84.84.84.84) port(85->11) udp_csum:43ec
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=7 cookie=0x9 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=7 cookie=0x9 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:17 tos:0 ttl:0 ip(83.83.83.83->84.84.84.84) port(85->86) udp_csum:43a1
|
||||
dnl
|
||||
NXT_PACKET_IN (xid=0x0): table_id=7 cookie=0x9 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 (via action) data_len=64 (unbuffered)
|
||||
NXT_PACKET_IN (xid=0x0): table_id=7 cookie=0x9 total_len=64 in_port=1 tun_id=0x6 reg0=0x1 reg1=0x2 reg2=0x3 reg3=0x4 reg4=0x5 reg5=0x0 reg6=0x0 reg7=0x0 (via action) data_len=64 (unbuffered)
|
||||
priority:0,tunnel:0,in_port:0000,tci(vlan:80,pcp:0) mac(80:81:81:81:81:81->82:82:82:82:82:82) type:0800 proto:17 tos:0 ttl:0 ip(83.83.83.83->84.84.84.84) port(85->86) udp_csum:43a1
|
||||
])
|
||||
|
||||
|
||||
Reference in New Issue
Block a user