Small corrections in code and Makefile

Makefile

@@ -1,6 +1,6 @@
 CXX=gcc
 
-CXXFLAGS=-Wall -Wextra -Werror -fstack-protector-all -pedantic -Wno-unused -std=c99
+CXXFLAGS=-Wall -Wextra -Werror -pedantic -fstack-protector-all -pedantic -std=c99
 SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-overflow=5 -Wformat=2
 
 SRC_DIR=src/
@@ -10,12 +10,12 @@ HEADERS=$(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)print
 ifneq ($(OS),Windows_NT)
 	SOURCE += $(SRC_DIR)udev.c
 	HEADERS += $(SRC_DIR)udev.h
+	OUTPUT=cpufetch	
 else
 	SANITY_FLAGS += -Wno-pedantic-ms-format
+	OUTPUT=cpufetch.exe
 endif
 
-OUTPUT=cpufetch
-
 all: $(OUTPUT)
 
 debug: CXXFLAGS += -g -O0

src/apic.c

@@ -29,8 +29,8 @@ unsigned char bit_scan_reverse(uint32_t* index, uint64_t mask) {
 }
 
 uint32_t create_mask(uint32_t num_entries, uint32_t *mask_width) {
-  uint32_t i;
-  uint64_t k;
+  uint32_t i = 0;
+  uint64_t k = 0;
 
   // NearestPo2(numEntries) is the nearest power of 2 integer that is not less than numEntries
   // The most significant bit of (numEntries * 2 -1) matches the above definition
@@ -91,7 +91,6 @@ bool fill_topo_masks_apic(struct topology** topo) {
   uint32_t core_plus_smt_id_max_cnt;
   uint32_t core_id_max_cnt;
   uint32_t smt_id_per_core_max_cnt;
-  uint32_t SMTIDPerCoreMaxCnt;
   
   cpuid(&eax, &ebx, &ecx, &edx);
   
@@ -117,7 +116,7 @@ bool fill_topo_masks_x2apic(struct topology** topo) {
   int32_t level_type;
   int32_t level_shift;
   
-  int32_t coreplus_smt_mask;
+  int32_t coreplus_smt_mask = 0;
   bool level2 = false;
   bool level1 = false;
   
@@ -173,7 +172,7 @@ bool fill_topo_masks_x2apic(struct topology** topo) {
   return true;
 }
 
-bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_core, uint32_t* apic_smt, struct topology** topo) {
+bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, struct topology** topo) {
   uint32_t sockets[64];
   uint32_t smt[64];
   
@@ -236,7 +235,7 @@ bool get_topology_from_apic(uint32_t cpuid_max_levels, struct topology** topo) {
     printf("[%2d] 0x%.8X\n", i, apic_smt[i]);*/
     
   
-  bool ret = build_topo_from_apic(apic_pkg, apic_core, apic_smt, topo);   
+  bool ret = build_topo_from_apic(apic_pkg, apic_smt, topo);   
   
   // Assumption: If we cant get smt_available, we assume it is equal to smt_supported...
   if(!x2apic_id) (*topo)->smt_supported = (*topo)->smt_available;

src/args.c

@@ -131,7 +131,6 @@ bool parse_color(char* optarg, struct colors** cs) {
 
 bool parse_args(int argc, char* argv[]) {
   int c;
-  int digit_optind = 0;
   int option_index = 0;  
   opterr = 0;
 

src/cpuid.c

@@ -272,7 +272,6 @@ struct topology* get_topology_info(struct cpuInfo* cpu) {
   uint32_t ebx = 0;
   uint32_t ecx = 0;
   uint32_t edx = 0;
-  int32_t type;
   
   // Ask the OS the total number of cores it sees
   // If we have one socket, it will be same as the cpuid,
@@ -386,8 +385,6 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
     // If its 0, we tried fetching a non existing cache
     if (cache_type > 0) {
       int32_t cache_level = (eax >>= 5) & 0x7;
-      int32_t cache_is_self_initializing = (eax >>= 3) & 0x1; // does not need SW initialization
-      int32_t cache_is_fully_associative = (eax >>= 1) & 0x1;
       uint32_t cache_sets = ecx + 1;
       uint32_t cache_coherency_line_size = (ebx & 0xFFF) + 1;
       uint32_t cache_physical_line_partitions = ((ebx >>= 12) & 0x3FF) + 1;
@@ -444,9 +441,15 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
     printBug("Invalid L1d size: %dKB", cach->L1d/1024);
     return NULL;
   }
-  if(cach->L2 != UNKNOWN && cach->L2 > 2 * 1048576) {
-    printBug("Invalid L2 size: %dMB", cach->L2/(1048576));
-    return NULL;
+  if(cach->L2 != UNKNOWN) {
+    if(cach->L3 != UNKNOWN && cach->L2 > 2 * 1048576) {
+      printBug("Invalid L2 size: %dMB", cach->L2/(1048576));
+      return NULL;
+    }
+    else if(cach->L2 > 100 * 1048576) {
+      printBug("Invalid L2 size: %dMB", cach->L2/(1048576));
+      return NULL;
+    }
   }
   if(cach->L3 != UNKNOWN && cach->L3 > 100 * 1048576) {
     printBug("Invalid L3 size: %dMB", cach->L3/(1048576));

src/main.c

@@ -6,14 +6,15 @@
 #include "cpuid.h"
 #include "global.h"
 
-static const char* VERSION = "0.510";
+static const char* VERSION = "0.6";
 
 void print_help(char *argv[]) {
   printf("Usage: %s [--version] [--help] [--levels] [--style fancy|retro|legacy] [--color 'R,G,B:R,G,B:R,G,B:R,G,B']\n\
 Options: \n\
-  --color    Set text color. 4 colors (in RGB format) must be specified in the form: R,G,B:R,G,B:...\n\
+  --color    Set a custom color scheme. 4 colors must be specified in RGB with the format: R,G,B:R,G,B:...\n\
              These colors correspond to the ASCII art color (2 colors) and for the text colors (next 2)\n\
              Suggested color (Intel): --color 15,125,194:230,230,230:40,150,220:230,230,230\n\
+             Suggested color (AMD):   --color 250,250,250:0,154,102:250,250,250:0,154,102\n\
   --style    Set the style of the ASCII art:\n\
     * fancy \n\
     * retro \n\

src/printer.c

@@ -15,11 +15,11 @@
 #define COL_INTEL_RETRO_1 "\x1b[36;1m"
 #define COL_INTEL_RETRO_2 "\x1b[37;1m"
 #define COL_AMD_FANCY_1   "\x1b[47;1m"
-#define COL_AMD_FANCY_2   "\x1b[41;1m"
+#define COL_AMD_FANCY_2   "\x1b[42;1m"
 #define COL_AMD_FANCY_3   "\x1b[37;1m"
-#define COL_AMD_FANCY_4   "\x1b[31;1m"
+#define COL_AMD_FANCY_4   "\x1b[32;1m"
 #define COL_AMD_RETRO_1   "\x1b[37;1m"
-#define COL_AMD_RETRO_2   "\x1b[31;1m"
+#define COL_AMD_RETRO_2   "\x1b[32;1m"
 #define RESET             "\x1b[m"
 
 #define TITLE_NAME        "Name:"
@@ -223,7 +223,7 @@ uint32_t get_next_attribute(struct ascii* art, uint32_t last_attr) {
   return last_attr;
 }
 
-void print_ascii_intel(struct ascii* art, STYLE s, uint32_t la) {
+void print_ascii_intel(struct ascii* art, uint32_t la) {
   bool flag = false;
   int attr_to_print = -1;
   uint32_t space_right;
@@ -260,7 +260,7 @@ void print_ascii_intel(struct ascii* art, STYLE s, uint32_t la) {
   }
 }
 
-void print_ascii_amd(struct ascii* art, STYLE s, uint32_t la) {
+void print_ascii_amd(struct ascii* art, uint32_t la) {
   int attr_to_print = -1;
   uint32_t space_right;
   uint32_t space_up = (NUMBER_OF_LINES - art->n_attributes_set)/2;
@@ -300,12 +300,12 @@ uint32_t longest_attribute_length(struct ascii* art) {
   return max;
 }
 
-void print_ascii(struct ascii* art, STYLE s) {
+void print_ascii(struct ascii* art) {
   uint32_t longest_attribute = longest_attribute_length(art);
   if(art->vendor == VENDOR_INTEL)
-    print_ascii_intel(art, s, longest_attribute);
+    print_ascii_intel(art, longest_attribute);
   else
-    print_ascii_amd(art, s, longest_attribute);
+    print_ascii_amd(art, longest_attribute);
 }
 
 bool print_cpufetch(struct cpuInfo* cpu, struct cache* cach, struct frequency* freq, struct topology* topo, STYLE s, struct colors* cs) {
@@ -355,7 +355,7 @@ bool print_cpufetch(struct cpuInfo* cpu, struct cache* cach, struct frequency* f
     return false;    
   }
 
-  print_ascii(art, s);
+  print_ascii(art);
 
   free(cpu_name);
   free(max_frequency);