Dr-Noob
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500ccfa871
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Stable version 0.7 heavily tested in many different CPUs
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2020-09-01 20:44:48 +02:00 |
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Dr-Noob
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877833db0a
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Dont fetch if smt is enabled if its not supported (AMD). Dont guess cache topology, fetch it from CPUID (AMD)
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2020-09-01 13:08:44 +02:00 |
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Dr-Noob
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5cca6df218
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Fix memory leaks. Add debug message when microarch is unknown
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2020-09-01 11:32:08 +02:00 |
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Dr-Noob
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de8952b4ea
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Fix bug which caused you couldnt use --version. Change --style to be more user friendly. Update --help
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2020-09-01 11:00:11 +02:00 |
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Dr-Noob
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1f80566f63
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New info to be displayed (uarch and process) instead of other info (sha, aes, sse)
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2020-09-01 09:37:53 +02:00 |
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Dr-Noob
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ab1416563c
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Fix PP in Ice Lake
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2020-08-31 18:27:32 +02:00 |
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Dr-Noob
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1a9c0546f2
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Add support for detecting AMD microarch
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2020-08-31 15:56:21 +02:00 |
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Dr-Noob
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35efdd8f2c
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Fix #26. Guess number of VPUs according to microarchitecture
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2020-08-31 14:04:41 +02:00 |
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Dr-Noob
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5148962fa3
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Add code to detect CPU microarchitecture (Intel only, at the moment)
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2020-08-31 13:18:25 +02:00 |
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Dr-Noob
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d998acdcdf
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Fix #25: Compute PP taking into account the number of sockets
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2020-08-31 09:33:39 +02:00 |
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Dr-Noob
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81a45628f0
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Code refactoring. Forgot to add verbose option to help
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2020-08-30 13:55:37 +02:00 |
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Dr-Noob
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4f98a5bccf
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Refactor previous commit
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2020-08-30 12:42:38 +02:00 |
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Dr-Noob
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dae0f678ad
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Fix #23. I tried fetching the cache topology in AMD but could not find a proper way, so the code fallback to two commits ago. cpufetch has to guess cache sizes except L3, which can be fetched. Since I have been trying many approaches and stuff, the code needs to be refactored
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2020-08-30 12:12:25 +02:00 |
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Dr-Noob
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69cc08759a
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Fix #21 and #22: Obtain the number of caches of every level instead of guessing them. It is done by fetching cache topology from apic. It works, but it needs a big refactoring. Moreover, it currently works only on Intel CPUs, so this breaks the cache in AMD.
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2020-08-29 21:51:14 +02:00 |
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Dr-Noob
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d8dad29a57
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Fix SMT bug in AMD. I would like to improve it, since Intel can use APIC with 0x1 and 0xB (extended) while AMD does with 0x1 and extended seems to be 0x1E. Add support to detect more than one L3 cache. This is not a very elegant solution, since we still assume that we have the same number of caches as caches in a given level. To fix it, cpufetch should know how many caches are in a given level (hint, Linux knows using shared_cpu_map)
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2020-08-29 15:42:56 +02:00 |
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Dr-Noob
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e08b60b1c8
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Project stopped until I have time to continue
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2020-07-12 19:08:38 +02:00 |
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Dr-Noob
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ad6c3c88ce
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Small corrections in code and Makefile
v0.6
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2020-07-12 15:39:34 +02:00 |
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Dr-Noob
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e114bde128
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Complete topology read in AMD
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2020-07-06 01:58:48 +02:00 |
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Dr-Noob
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7164409ca2
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Add legacy style (for Windows) and make it the default for Windows. Add verbose flag
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2020-07-06 01:30:14 +02:00 |
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Dr-Noob
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08f79bb914
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Fix compilation in Windows and add support for bind to specific cores. Separate APIC code in other file
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2020-07-06 01:16:59 +02:00 |
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Dr-Noob
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b457c86100
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Add support for obtaining topology in old processors (with CPUID less than 0xB)
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2020-07-05 19:59:55 +02:00 |
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Dr-Noob
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e5d86289b5
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Use APIC to obtain topology. This is interesting because this will allow us to obtain it even on older CPUs (without CPUID 0xB) (will be added in future commits)
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2020-07-05 16:52:41 +02:00 |
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Dr-Noob
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c6c4d8b6fd
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Fix spaces bug in CPU name
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2020-07-03 19:42:05 +02:00 |
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Dr-Noob
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c8fde107dd
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Fix ascii logo in AMD. Fix output on CPUs without L3
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2020-07-03 16:24:14 +02:00 |
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Dr-Noob
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b076189b32
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Add support to detect if HT/SMT is enabled or disabled
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2020-07-03 16:11:09 +02:00 |
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Dr-Noob
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d43229359a
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Support for 4 colors with --color (2 for ascii, 2 for text)
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2020-07-03 09:42:30 +02:00 |
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Dr-Noob
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ba047c76e3
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Add two different styles. The old one is now called retro, and the new one, which is the default, is called fancy
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2020-07-02 18:53:28 +02:00 |
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Dr-Noob
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942a86c04f
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Remove styles and add option to specify custom color output in RGB format
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2020-07-02 16:14:37 +02:00 |
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Dr-Noob
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ea338a68c8
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Forgot to support AMD in printer
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2020-06-29 17:32:50 +02:00 |
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Dr-Noob
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d7b7e2b62d
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Support printing dual socket. Fix bug where cache sizes were not displayed correctly (they were truncated)
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2020-06-29 17:13:37 +02:00 |
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Dr-Noob
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941bf35d03
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Big refactoring. Move ascii managment to printer. Mix extended and standart cpuid functions in cpuid file. Old cpuid renamed to cpuid_asm. Store cpu name in cpuInfo struct
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2020-06-28 15:51:30 +02:00 |
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Dr-Noob
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131d860de6
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Print total cache sizes (for L1 and L2, but also for L3 in case we run in dual socket!)
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2020-06-28 12:47:03 +02:00 |
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Dr-Noob
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92992be225
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Support for multi socket systems (only information gathering, not printing)
v0.410
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2020-06-22 18:04:24 +02:00 |
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Dr-Noob
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698274e44c
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Fix bug and memory leak
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2020-06-22 18:00:45 +02:00 |
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Dr-Noob
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7fee305e8b
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Little fixes
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2020-06-22 15:30:05 +02:00 |
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Dr-Noob
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1ce6b97bec
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Fix topology in AMD, using extended level to fetch it
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2020-06-22 15:04:32 +02:00 |
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Dr-Noob
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8211f24f46
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Fix cache in AMD, using extended level
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2020-06-22 13:50:00 +02:00 |
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Dr-Noob
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0725e9d876
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Add --levels option
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2020-06-22 13:17:00 +02:00 |
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Dr-Noob
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a2dab8129c
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Use standart types instead of int/long in specific files. This fixes a problem in Windows, were PP was not computed correctly. Compiling with C99
v0.47
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2020-06-22 12:47:14 +02:00 |
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Dr-Noob
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08ce1de122
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Add fallback in Linux in case we cant get the freq from cpuid, using udev (welcome back, udev...)
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2020-06-22 12:05:04 +02:00 |
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Dr-Noob
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10cf53479e
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Fix small bug in get_str_topology. Fix #15
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2020-06-21 15:55:14 +02:00 |
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Dr-Noob
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ce4ecd7af4
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Fix bug introduced when using stdbool instead of ints
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2020-06-21 13:41:14 +02:00 |
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Dr-Noob
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1435978b37
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Add release and debug targets in Makefile. Improve robustness by checking cache sizes and snprintf returns
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2020-06-21 13:37:44 +02:00 |
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Dr-Noob
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0087453eda
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Refactoring in printer
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2020-06-21 12:43:51 +02:00 |
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Dr-Noob
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0cba7b4348
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Add "none" style (useful for non colored terminals). Refactoring in printer
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2020-06-21 11:07:35 +02:00 |
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Dr-Noob
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a1496278c3
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Fix bug: remove spaces between CPU name in certain processors
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2020-06-21 01:48:29 +02:00 |
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Dr-Noob
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525cf1a76f
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Get number of cores (Intel only) with cpuid. This removes sysconf dependency. This implementation breaks cpufetch in NUMA environments
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2020-06-20 20:54:38 +02:00 |
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Dr-Noob
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6ad5f65c34
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Improve error checking. Add partial support for verbose output
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2020-06-20 19:21:07 +02:00 |
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Dr-Noob
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b81d611282
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Fetch freq from cpuid, instead of asking Linux (using /proc). This finally removes udev dependency. However, the support of cpuid 0x16 is limited, so this may break cpufetch on some systems
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2020-06-20 13:24:50 +02:00 |
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Dr-Noob
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04a2fef2a2
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Fetch cache info from cpuid, instead of asking Linux (using /proc)
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2020-06-20 12:15:59 +02:00 |
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